參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 48/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
52
Bit 09
: Fast B-to-B En (R) – Fast Back-to-Back Enable. This bit is hardwired to 0 to indicate that the SiI3124
does not support Fast Back-to-Back operations as bus master.
Bit 08
: SERR Enable (R/W) – SERR Output Enable. This bit set enables the SiI3124 to drive the PCI SERR#
pin when it detects an address parity error. The Parity Error Response bit (06) must also be set to enable
SERR# reporting.
Bit 07
: Addr Step (R) – Address Stepping Enable. This bit is hardwired to 1 to indicate that the SiI3124 does
support Address Stepping.
Bit 06
: Par Error Resp (R/W) – Parity Error Response Enable. This bit set enables the SiI3124 to respond to
parity errors on the PCI bus. If this bit is cleared, the SiI3124 will ignore PCI parity errors. The Detected Parity
Error (bit 31) in this register is set regardless of the state of this bit.
Bit 05
: VGA Palette (R/W) – VGA Palette Snoop Enable. The feature is not implemented and this bit should
always be written as 0.
Bit 04
: Mem Wr & Inv (R) – Memory Write and Invalidate Enable. This bit enables the use of Memory Write and
Invalidate bus cycles.
Bit 03
: Special Cycles (R/W) – Special Cycles Enable. This bit should always be written with 0 to indicate that
the SiI3124 does not respond to Special Cycles.
Bit 02
: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI3124 to act as PCI bus master. A
PCI-X Split Completion cycle may be initiated even if this bit is set to 0.
Bit 01
: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI3124 to respond to PCI
memory space accesses.
Bit 00
: I/O Space (R/W) – I/O Space Enable. This bit set enables the SiI3124 to respond to PCI I/O space
accesses.
7.1.3
PCI Class Code – Revision ID
Address Offset: 08H
Access Type: Read/Write
Reset Value: 0x0180_0002
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Class Code
Revision ID
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit [31:08]
: PCI Class Code (R) – PCI Class Code. This value in this bit field is one of the following three:
the default value of 018000h for Mass Storage Class.
the value loaded from an external memory device; if an external memory device – Flash or EEPROM – is
present with the correct signature, the PCI Class Code is loaded from that device after reset. See section 6
on page 44.
system programmed value; if bit 0 of the Configuration register (48H) is set the PCI Class Code is system
programmable.
Bit [07:00]
: Revision ID (R) – Chip Revision ID. This bit field is hardwired to indicate the revision level of the chip
design; revision 02H is defined by this specification.
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