參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 64/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
67
7.3 Internal Register Space – Base Address 1
These registers are 32 bits wide and are the Port Registers and LRAM of the SiI3124. Access to these registers is through the
PCI Memory space. Register descriptions that follow specify the address offset for Port 0; subsequent port registers are at
2000H offset increments, i.e., the upper 2 bits of the 15-bit address offset is the Port number (0-3).
Address Offset
Register Name
000H-F7FH
Port 0 LRAM Slots
F80H-FFFH
Port Multiplier Device Status/QActive Registers
1000H
Write: Port 0 Control Set / Read: Port 0 Status
1004H
Write: Port 0 Control Clear
1008H
Port 0 Interrupt Status
100CH
Reserved
1010H
Port 0 Interrupt Enable Set
1014H
Port 0 Interrupt Enable Clear
1018H
Reserved
101CH
32-bit Activation Upper Address
1020H
Port 0 Command Execution FIFO
1024H
Port 0 Command Error
1028H
Port 0 FIS Configuration
102CH
Port 0 PCI(X) Request FIFO Threshold
1030H-103FH
Reserved
1040H
Port 0 8B/10B Decode Error Counter
1044H
Port 0 CRC Error Counter
1048H
Port 0 Handshake Error Counter
104CH
Reserved
1050H
Port PHY Configuration
1054H-17FFH
Reserved
1800H
Port 0 Slot Status
1804H-1BFFH
Reserved
1C00H-1CF7H
Command Activation Registers
1CF8H-1E03H
Reserved
1E04H
Port Context Register
1E08H-1EFFH
Reserved
1F00H
Port 0 SControl
1F04H
Port 0 SStatus
1F08H
Port 0 SError
1F0CH
Port 0 SActive (indirect location)
1F10H-1FFFH
Reserved
2000H-3FFFH
Port 1 Registers mapped as above
4000H-5FFFH
Port 2 Registers mapped as above
6000H-7FFFH
Port 3 Registers mapped as above
Table 7-4 SiI3124 Internal Register Space – Base Address 1
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