參數(shù)資料
型號(hào): ORT8850L-3BM680C
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 78/105頁(yè)
文件大?。?/td> 0K
描述: IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告: Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝: 24
系列: *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
74
LVDS Receiver Buffer Requirements
Table 30. Receiver DC Data
1
Table 31. LVDS Operating Parameters
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Input Voltage Range, VIA or VIB
VI
VGPD < 925 mV
DC – 1 MHz
0.0
1.2
2.4
V
Input Differential Threshold
VIDTH
VGPD < 925 mV
450 MHz
–100
100
mV
Input Differential Hysteresis
VHYST
(+VIDTHH) – (–VIDTHL)
25
mV
Receiver Differential Input Impedance
RIN
With build-in termination,
center-tapped
80
100
120
Ω
1. VDD = 3.1V - 3.5V, 0 °C -125 °C.
Parameter
Test Conditions
Min.
Normal
Max.
Units
Transmit Termination Resistor
80
100
120
Ω
Receiver Termination Resistor
80
100
120
Ω
Temperature Range
–40
125
C
Power Supply VDD33
3.0
3.6
V
Power Supply VDD15
1.425
1.575
V
Power Supply VSS
0
V
Note: Under worst-case operating conditions, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time
without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage.
The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
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