參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 16/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
18
output. Although all TOH bytes from the 12 STS-1s are transferred into the device from each serial port, not all of
them get inserted in the frame. There are three hard coded exceptions to the TOH byte insertion:
Framing bytes (A1/A2 of all STS-1s) are not inserted from the serial input bus. Instead, they can always be
regenerated.
Parity byte (B1 of STS#1) is not inserted from the serial input bus. Instead, it is always recalculated (the 11 bytes
following B1 are replaced with all zeros).
Pointer bytes (H1/H2/H3 of all STS-1s) are not inserted from the serial input bus. Instead, they always ow trans-
parently from parallel input to LVDS output.
The data stream is scrambled in the transmit direction and descrambled in the receive direction using a frame syn-
chronous scrambler of sequence length 127, operating at the line rate. The generating polynomial for the scrambler
is 1+x
6+x7. The polynomial conforms to the standard SONET STS-12 data format. The scrambler is reset to
'1111111' on the rst byte of the SPE (byte following the Z0 byte in the 12th STS-1). That byte and all subsequent
bytes to be scrambled are XOR'd, with the output from the bytewise scrambler. The scrambler runs continuously
from that byte, through the remainder of the frame. A1, A2, and J0/Z0 bytes are not scrambled. The B1 byte is cal-
culated (in both transmitter and receiver) on the non-scrambled data. There is a global scrambler/descrambler dis-
able feature, allowing the user to disable the scrambler of the transmitter and the descrambler of the receiver.
Following the scrambler block, byte wide data streams are sent to the HSI macrocell.
Receive STM Macrocell Logic - Overview
In the receive direction (backplane to the FPGA interface) each STM macrocell receives four byte wide data
streams at the reference clock rate (i.e., 8 X SYS_CLK_[P:N] in normal operation) and four associated clocks from
the HSI. The incoming streams are framed and (optionally) descrambled before they are written into a FIFO which
absorbs phase and delay variations and allows the shift to system clock and optionally allows frames to be aligned
both between quads and between streams on the same quad. Optionally, the pointer interpreter logic will then put
the STS SPEs into a small elastic store from which the pointer generator will produce four byte wide STS-12
streams of data that are aligned to the system timing pulse.
The alignment FIFO depth allows for 18 clocks of difference in the arriving A1/A2. If any of the channels in an align-
ment group are too far out of alignment for the FIFO to absorb the difference an alarm register will indicate the
error. Alarm indicators can be programmed to trigger an alarm at different levels of misalignment.
The multichannel alignment option allows separate SERDES data channels to be byte aligned based on the
SONET A1/A2 bytes. Data is written into the alignment FIFO using the per channel recovered clocks from the SER-
DES channel. Data is always read from the alignment FIFO using the local reference clock. (SYS_CLK pin,
FPGA_SYS CLK)
SERDES data channels can be placed into an alignment group by 2, by 4, or all 8. In by 2 mode, channels AA and
BA, AB and BB, AC and BC, and AD and BD are byte aligned. In by 4 mode channels AA, AB, AC, AD and BA, BB,
BC, BD are byte aligned. In the by 8 mode all of the channels are byte aligned.
After the alignment FIFO the receive data can optionally go through the pointer interpreter and pointer mover. The
pointer interpreter will identify the SONET payload envelope (SPE) and the C1(J0) bytes and the J1 bytes. For data
applications where the user is simply using SONET to carry user dened cells in the payload the SPE signal is very
useful as an enable to the cell processor. C1J1 for data applications can be ignored. If the pointer interpreter and
pointer mover are bypassed, then the SPE and C1J1 signals to the FPGA logic will be always '0'.In the ORT8850
each frame consists of 12 STS-1 format sub-frames. Thus, in the SPE region, there are 12 J1 pulses, one for each
STS-1. There is one C1(J0) (current SONET specications use J0 instead of C1 as section trace to identify each
STS-1 in an STS-N) pulse in the TOH area for one frame. Thus, there are a total of 12 J1 pulses and one C1(J0)
pulse per frame. The C1(J0) pulse is coincident with the J0 of STS-1 #1 which is the rst byte following the last A2
byte.
With the pointer interpreter option enabled, the SPE ag is active when the data stream is in SPE area. SPE
behavior is dependent on pointer movement and concatenation. Note: in the TOH area, H3 can also carry valid
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