參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 27/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
28
A1 and A2 framing bits are inserted (errored bits may optionally be inserted)
The bit interleaved parity bit (B1) for the previously transmitted frame is inserted
The data is scrambled using the standard STS-12 polynomial (optional)
A parallel to serial conversion is performed on the data
The serial data is broadcast to the work and protect LVDS buffers
These processing steps are described in more detail in the following sections. A block diagram of the transmit path
logic is shown in Figure 12. All processing except the parallel to serial conversion is optional. If all processing except
the SERDES is deselected, the device is said to be operating in the "bypass" mode.
Figure 12. Basic Logic Blocks, Transmit Path, Single Channel
Parity Checking
Parity error checking is implemented on each of the four parallel input buses on each STM quad (A & B) on a per
channel basis. "Even" or "Odd" parity can be selected by setting a control register bit. Upon detection of an error,
an alarm bit in a status register is set.
There is also even parity error checking on each of the four TOH serial input ports on a per channel basis. Upon
detection of an error, an alarm bit in a status register is set.
TOH Byte Modication
The transport overhead bytes of the SONET frame can be used for in-band conguration, service, and manage-
ment since it is carried along the same channel as data. In the ORT8850 in-band signaling can be efciently uti-
lized, since the total cost of overhead is only 3.3%. TOH data can be inserted into the transmit data stream in one
of two ways, the Transparent Insertion mode and the Serial TOH Insertion mode. The overhead bytes in an STS-1
header are shown in Figure 13. (The path overhead bytes are in the SPE.)
Logic Common to Both Quads
Note:
xx=[AA, AB,…BD]
(from control
registers)
SYS_FP
DINxx [7:0]
DINxx _PAR
TXDxx_W_[P:N]
TXDxx_P_[P:N]
8
2
FPGA
Logic
Embedded Core
SONET Logic
Backplane
Serial
Links
I/O MUXs
And LVDS
Buffers
To other
7 channels
LVDS
Buffer
LVDS
Buffer
2
Parallel
To
Serial
Convert
Scrambler
(optional)
Parity
Check
Repeater
(for
STS 3)
TOH
Insert
(opt.)
A1A2
Insert
(opt.)
B1
Insert
(opt.)
B1
Calc.
Prev.
B1
Hold
TOH
Serial
To
Parallel
Convert
Insert
A1A2
Error
Insert
B1
Error
Odd or Even
(from control
register)
PLL
TX_TOH_CK_EN
TOH_Inxx
77.78 MHz
622 MHz
FPGA_SYSCLK
2
LVDS
Buffer
SYS_CLK_[P:N]
TOH_CLK
To other
7 channels
To other
7 channels
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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