參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 45/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
44
SPE and C1J1 Identication
In the ORT8850 each frame can be considered as 12 STS-1s. In the SPE region, there are 12 J1 pulses for each
STS-1s. There is one C1(J0, new SONET specications use J0 instead of C1 as section trace to identify each STS-
1 in an STS-N) pulse in the TOH area for one frame. Thus, for non concatenated data there are a total of 12 J1
pulses and one C1(J0) pulse per frame. The C1(J0) pulse is coincident with the J0 of STS-1 #1.
The pointer interpreter identies the payload area of each frame. The SPE ag is active when the data stream is in
SPE area. SPE behavior is dependent on pointer movement and concatenation. Note that in the TOH area, H3 can
also carry valid data. When valid SPE data is carried in this H3 slot, SPE is high in this particular TOH time slot. In
the SPE region, if there is no valid data during any SPE column, the SPE signal will be set to low. SPE allows a
pointer processor to extract payload without interpreting the pointers.
Figure 23. SPE and C1J1 Functionality for STS -12
The following rules are observed for generating SPE and C1J1 signals:
On occurrence of AIS-P on any of the STS-1, there is no corresponding J1 pulse.
In case of concatenated payloads (up to STS48c), only the head STS-1 of the group has an associated J1 pulse.
The C1J1 signal tracks any pointer movements.
This behavior is illustrated in the following gure. Note that the actual bit positions are dependent on the actual pay-
load conguration and offset.
Figure 24. SPE and C1J1 Signals
Pointer Mover
After the pointer interpreter comes the pointer mover block. There is a separate pointer mover for the two SONET
framer quads, A and B, each of which handles up to one STS-48 (four channels) The K1/K2 bytes and H1-SS bits
are also passed through to the pointer generator so that the FPGA can receive them. The pointer mover handles
both concatenations inside the STS-12, and to other STS-12s inside the core. Use of this block is optional, as dis-
cussed in a later section.
SPE
C1J1
Description
0
TOH information excluding C1(J0) of STS-1 #1.
0
1
Position of C1(J0) of STS-1 #1 (one per frame). Typically used to provide a unique link identication
(256 possible unique links) to help ensure cards are connected into the backplane correctly or cables
are connected correctly.
1
0
SPE information excluding the 12 J1 bytes.
1
Position of the 12 J1 bytes.
STS-12
TOH ROW # 1
SPE ROW # 1
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 J0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0
STS-12
SPE
C1J1
C1 PULSE
J1 PULSE OF
3RD STS-1
first SPE BYTES OF THE
12 STS-1S
1 2
3 4
5 6 7
8 9 10 11 12
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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