參數(shù)資料
型號: ORT8850L-3BM680C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 53/105頁
文件大小: 0K
描述: IC FPSC TRANSCEIVER 8CH 680-BGA
產品變化通告: Product Discontinuation 01/Aug/2011
標準包裝: 24
系列: *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
51
tions. (The clock edge on which data is latched in the core is hard wired to be the falling edge.) Since the falling
edge of the clock (FPGA_CLK) at the FPGA latch occurs after the next data byte is launched, the delay from the
interface to the FPGA latch must be large enough that an acceptable hold time margin is obtained. However the
maximum propagation delay is fairly large, so a half cycle approach might lead to setup time problems.
Figure 27. Full Cycle, Alignment FIFO Bypass Mode Output Conguration and Timing (-1 Speed Grade)
D
-
Q
-
Δt
Note: xx = [AA, AB, ..., BD]
DOUTxx[7:0]
Embedded
Core
FPGA
Logic
3.0 ns
Secondary Clock
0.5 ns
1.3 ns
RETIME_CLK
HSI_CLK
a. Configuration
b. Timing (ns)
FPGA_CLK
CDR_CLK_xx
RETIME_CLK
FPGA_CLK
Data Valid
DOUTxx[7:0]
0.0
4.7
9.4
14.1
18.8
0.8
5.5
10.2
14.9
19.6
2.5
7.2
11.9
16.6
Launch
Hold
Capture
tprop_max = 4.7
tprop_min = 0.8
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