參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 71/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
68
30037*
3004F
30067
3007F
30097
300AF
300C7
300DF
[0]
R/W
Bypass pointer
mover
0
0 = use pointer mover
1 = Bypass pointer mover.
[1]
R/W
Bypass pointer
mover and align-
ment FIFO
0
0 = uses alignment FIFO and pointer mover
1 = Bypass alignment FIFO and pointer mover.
[2]
Enable work/pro-
tect channels
0
Bit to control the LVDS receivers to CDR.
0 = Use LVDS receivers from HSI work channels.
1 = Use LVDS receivers from HSI protect channels.
[3:4]
R
Multichannel
alignment control
00
00 = No alignment.
10 = Align with twin (i.e., STM B stream A).
01 = Align with all 4 (i.e., STM A all streams).
11 = Align with all 8 (i.e., STM A and B all streams).
[5]
R
RX path SONET
framer
0
0 = Enable framer.
1 = Disable SONET framing data is passed through
[6-7]
-
Not Used
0
300E0
[0]
R/W
Reserved
0
Reserved, must be set to 0.
[1]
R/W
CDR control
register
0
Always set to zero
[2]
-
Not Used
0
[3]
R/W
CDR control
register
0
When set to 1, controls bypass of 16 PLL generated
phases with 16 low-speed phases.
[4]
R/W
CDR control
register
0
Enables CDR loopback.
0 = No loopback.
1 = Loopback TX to RX.
[5]
R/W
CDR control
register
0
Enables bypassing of the internal 622 MHz clock with
TSTCLK. Must be used for simulation
0 = Use PLL.
1 = Bypass PLL (uses TSTCLK as reference clock).
[6]
R/W
CDR control
register
0
Enables CDR test mode. Initiates CDR’s built-in self-test:
0 = Regular mode.
1 = Test mode.
[7]
-
Not Used
0
300E1
[0:7]
R/W
Half Rate
Per Channel select for half rate mode can only be used in
pure bypass mode. Bit 7 is for channel BD, bit 6 is for BC
etc.
0 = full rate
1 = half rate
300E2
[0:7]
R/W
Quad Rate
Per Channel select for quad rate mode can only be used in
pure bypass mode. Bit 7 is for channel BD, bit 6 is for BC
etc.
0 = full rate
1 = quad rate
* For Channels AA, AB, AC, AD, BA, BB, BC, BD respectively
Note: Registers at addresses
≥ 300E3 must remain at their default (reset) settings and must not be changed by the user.
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT9303 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY
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