參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 74/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
70
Power Supply Decoupling LC Circuit
The 850 MHz HSI macro contains both analog and digital circuitry. The data recovery function, for example, is
implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its
850 MHz reference frequency. The internal analog phase-locked loop contains a voltage-controlled oscillator. This
circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic
gates and parasitic inductive elements. Generated noise that contains frequency components beyond the band-
width of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will
impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit ele-
ments.
Additional power supply ltering in the form of a LC lter section will be used between the power supply source and
these device pins as shown in Figure 32. The corner frequency of the LC lter is chosen based on the power supply
switching frequency, which is between 100 kHz and 300 kHz in most applications.
Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cut-off frequency of the LC lter. For
example, the cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capaci-
tor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency
signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the
device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended lter for
the HSI macro is shown below: L = 4.7H, RL = 1
Ω, C1 = 0.01F, C2 = 0.01F, C3 = 4.7F.
Figure 32. Sample Power Supply Filter Network for Analog HSI Power Supply Pins
5-9344(F)
If the programmable PLLs on the FPGA portion of the device are to be used, then the VDD33 supply must isolated
in the same way. More information on this and other requirements for the FPGA PLLs can be found in technical
note TN1011,
ORCA Series 4 I/O Tuning via PLL available on the Lattice web site at www.latticesemi.com.
C2
+
C3
+
TO DEVICE
PLL_VSSA
C1
+
FROM POWER
SUPPLY SOURCE
L
VDDA_STM
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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