參數(shù)資料
型號： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 57/105頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
55
Figure 31 shows the timing for sending TOH data from the FPGA logic to the Core. As in the earlier input example,
the constraints on the data are specied in terms of setup and hold times on the data at the interface relative to the
clock at the interface. In the case shown, launch and capture occur on different clock edges (rising edge in the
FPGA). Data is captured before the next data is launched, so there will be no hold margin problem. Launched data
also has nearly a full clock period to become stable at the capture latch, so setup margin should not be a problem
for the timing relationships assumed in the example. Actual timing analysis should be performed for each applica-
tion because of the wide range of possible skew values.
Figure 31. Half Cycle, TOH Input Conguration and Timing (-1 Speed Grade)
Q
+
D
-
Δt
Embedded
Core
FPGA
Logic
Secondary Clock
1.8 ns
ASB_IN_TOH_CLK
a. Configuration
b. Timing (ns)
FPGA_CLK
TOH_CLK
Note: xx = [AA, AB, ..., BD]
TOH_INxx
±3.0 ns skew
+2.0 ns assumed
TOH_CLK
0.0
4.7
9.4
Capture
14.1
FPGA_CLK
2.0
6.7
11.4
16.1
Launch
1.8
6.5
11.2
15.9
Hold
Data
Valid
ASB_IN_TOH_CLK
TOH_INxx
Requirements on
hold time = 1.8
setup time = 0.0
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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