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參數(shù)資料
| 型號： | ORT8850L-3BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 13/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
15
LVDS Reference Clock
The reference clock for the ORT8850 SERDES is an LVDS input (SYS_CLK_[P:N]). This reference clock can run in
the range from 63.00 MHz to 106.25 MHz and is used to clock the entire Embedded Core. This clock is also avail-
able in the FPGA interface as the output signal FPGA_SYSCLK at the Embedded Core/FPGA Logic interface.
The supported range of reference clock frequencies will drive the internal and link serial rates from 504 MHz to 850
MHz. For standard SONET applications a reference clock rate of 77.76 MHz will allow the ORT8850 to communi-
cate with standard SONET devices. If the ORT8850 is communicating with another ORT8850, the reference clock
can run anywhere in the dened range. When using a non 77.76 MHz reference clock, the frame pulse will now
need to be derived from the non standard rate thus making the frame pulse rate not 8 kHz, but rather a single clock
pulse every 9720 clock cycles.
System Considerations for Reference Clock Distribution
There are two main system clocking architectures that can be used with the ORT8850 at the system level to pro-
vide the LVDS reference clocks. The recommended approach is to distribute a single reference clock to all boards.
However, independent clocks can be used on each board provided that they are matched with sufcient accuracy
and the alignment is not used. These two approaches are summarized in the following paragraphs
Distributed Clocking
A distributed clock architecture, shown in Figure 5, uses a single source for the system reference clock. This single
source drives all devices on both the line and switch sides of the backplane. Typically this is a lower speed clock
such as a 19.44 MHz signal. An external PLL on each board or and internal ORT8850 FPGA PLL is then used to
multiply the clock to the desired reference clock rate (i.e. by 4x to 77.76 MHz if the distributed clock is at 19.44
MHz). Using this type of clock architecture the ORT8850 data channels are fully synchronous and no domain trans-
fer is required from the transmitter to the receiver.
Figure 5. Distributed Clock Architecture
Independent Clocking
An independent clock architecture uses independent clock sources on each ORT8850 board. With this architec-
ture, for the SERDES to sample correctly the independent oscillators must be within reference clock tolerance
requirements for the Clock and Data Recovery (CDR) to correctly sample the incoming data and recover data and
clock. The local reference clock and the recovered clock will not be synchronous since they are created from a dif-
ferent source. The alignment FIFO uses the recovered clock for write and the local reference clock for read. Due to
19.44 Mhz.
Oscillator
Fabric
Cards
Port
Cards
System Diagram
19.44 Mhz
Clock Source
77.76 Mhz
Clock (Differential)
SYS_CLK_P
SYS_CLK_N
PIO_OUT_N
PIO_OUT_P
FPGA
PPLL (x4)
Buffer
ORT8850
(SERDES at
622 Mbps)
FPGA
LVDS
PIO
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相關代理商/技術參數(shù) |
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| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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