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| 型號(hào)： | ORT8850L-3BM680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 33/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 8CH 680-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT8850 Data Sheet
33
Table 10. Transmitter TOH on LVDS Output (TOH Insert Mode)
Repeater
This block is essentially the inverse of the sampler block discussed in the receive path description section. It
receives byte-wide STS-12 rate data from the TOH insert block. In order to support the STS-3 mode of operation,
the HSI (622 Mbits/s) can be connected to a slower speed device (e.g., 155 Mbits/s). The purpose of this block is to
rearrange the data being fed to the HSI so that each bit is transmitted four times, thus simulating 155 Mbits/s serial
data. In STS-3 mode, the incoming STS-12 stream is composed of four identical STS-3s so only every fourth byte
is used. The bit expansion process takes a single byte and stretches it to take up 4 bytes each consisting of 4 cop-
ies of the 8 bits from the original byte.
A1/A2 Processing
The A1 and A2 bytes provide a special framing pattern that indicates where a STS-1 begins in a bit stream. All 12
A1 bytes of each STS-12 are set to 0xF6, and all 12 A2 bytes are set to 0x28 automatically by the SONET framer.
The latency from the transmit of the rst bit of the A1 byte at the device output pins from the system frame pulse on
the FPGA interface is between ve to seven clock cycles of the reference clock (FPGA_SYSCLK).
The A1 and A2 bytes can also be intentionally corrupted for testing by the A1/A2 error insert control register
(0x3000D, 0x3000E). Only the last A1 and rst A2 are corrupted. When A1/A2 corruption detection is set for a par-
ticular channel, the A1/A2 values in the corrupted A1/A2 value registers are sent for the number of frames dened
in the corrupted A1/A2 frame count register (0x3000C). When the corrupted A1/A2 frame count register is set to
0x00, A1/A2 corruption will continue until the A1/A2 error insert register is cleared.
The ORT8850 device only has one control register to set the A1/A2 bytes as well as the number of frames of cor-
ruption. To insert the corrupted A1/A2 each channel has an enable A1/A2 insert register. When the per channel
error insert register bit is set, the A1/A2 values are corrupted for the number specied in the number of frames to
corrupt. To insert errors again, the per channel error insert register bit must be cleared, and set again.
It is also possible to not insert the A1/A2 framing bytes using the per channel register bit “disable A1/A2 insert.”
B1 Processing
In the transmit direction a bit interleaved parity (BIP-8) error check set for even parity over all the bits of an STS-1
frame B1 is dened for the rst STS-1 in an STS-12 only, the B1 calculation block computes a BIP-8 code, using
even parity over all bits of the previous STS-12 frame after scrambling and is inserted in the B1 byte of the current
STS-12 frame before scrambling.
Per-bit B1 corruption is controlled by the force BIP-8 corruption register (0x3000F). For any bit set in this register,
the corresponding bit in the calculated BIP-8 is inverted before insertion into the B1 byte position. Each stream has
an independent fault insert register that enables the inversion of the B1 bytes. B1 bytes in all other STS- 1s in the
stream are lled with zeros.
It is also possible to not insert the B1 byte using the per channel register bit "disable B1 insert."
A1
A2
J0
B1
0
E1
F1
D1
D2
D3
H1
H2
H3
B2
K1
K2
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1
M0
E2
Regenerated bytes.
Bytes optionally inserted from TOH serial port data or transparently forwarded from parallel input port
Bytes transparently forwarded from parallel input port
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| ORT8850L-3BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT9303 | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303B | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303BL | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
| ORT9303G | 制造商:BOT 制造商全稱:Bedford Opto Technology Ltd. 功能描述:3 ELEMENT PCB MOUNT 1.8mm LED ARRAY |
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