參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 14/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
16
this feature the alignment FIFO cannot be used with this clock architecture. The recovered clock is used for all
receive timing in the embedded core and supplied to the FPGA logic which must provide the clock domain transfer
functionality.
Figure 6. Independent Clock Architecture
SONET Bypass Mode
It is possible to utilize only the serializer and deserializer (SERDES) blocks in the ORT8850 and to bypass all of the
SONET framing and scrambling/descrambling. In this mode the parallel data from the FPGA is serialized and sent
out the LVDS pins. The serial data in the receive direction will be run through the SERDES and then received as
parallel data with a recovered clock into the FPGA.
In the SONET Bypass mode there exists half and quarter rate selection options. Half rate allows the SERDES to
operate at 4x the reference clock. When using half rate mode only the bits 7:4 of the parallel FPGA bus are utilized.
Quarter rate allows the SERDES to operate at 2x the reference clock. When using quarter rate mode only bits 7:6
of the parallel FPGA bus are utilized. Half rate and quarter rate are selectable per channel and can be mixed per
channel so that some channels can run in full rate mode while others operate in half rate mode and still others
operate in quarter rate mode.
As shown in Table 3, 63.00 MHz is the slowest reference clock and 106.25 MHz is the fastest reference clock fre-
quency supported. For all three modes, all bandwidths within the reference clock limits are supported. Note that
there are gaps between the bandwidths supported in the three modes.
Table 3. SONET Bypass Mode Bandwidth Options
In the SONET Bypass mode a 1's density function similar to SONET scrambling must be implemented in the FPGA
logic to assure reliable clock recovery at the receiver.
Reference Clock
Full Mode
Half Mode
Bits [7:4] Used
Quarter Mode
Bits [7:6] Used
63
504.00 Mbits/s
252.00 Mbits/s
126.00 Mbits/s
77.76
622.08Mbits/s
311.04Mbits/s
155.52Mbits/s
106.25
850.00 Mbits/s
425.00 Mbits/s
212.50 Mbits/s
Fabric
Cards
Port
Cards
System Diagram
Osc.
Board
Details
77.76 Mhz
Oscillator
SYS_CLK_P
SYS_CLK_N
* Examples of
Typical Board
Components
LVDS
Buffer
or
77.76 Mhz
Differential
Output
Oscillator
TI
SN65LVDS31D*
Conner
Winfield
HC54R8*
ORT8850
(SERDES at
622 Mbps)
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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