參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 24/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
25
Backplane Transceiver Core Detailed Description
SONET Logic Blocks, Detailed Description
The following sections describe the data processing performed in the SONET logic blocks. A 622 Mbits/s is
assumed in the descriptions however, as noted in the Overview sections, the ORT8850 can operate at variable
rates up to 850 Mbits/s. At a top level, the descriptions are separated into processing in the transmit path (FPGA to
serial link) and processing in the receive path (serial link to FPGA). A top level drawing of the two data paths and
associated clocks is shown in Figure 11. The various processing options are selected by setting bits in control reg-
isters and status information is written to status registers. Both types of registers can be written and/or read from
the System Bus or the MicroProcessor Interface (MPI). Memory maps and descriptions for the registers are given
Figure 11. ORT8850 Top Level Data Flow
0x30038
0x07
Channel AB in functional mode without AIS-L
0x30050
0x07
Channel AC in functional mode without AIS-L
0x30068
0x07
Channel AD in functional mode without AIS-L
0x30080
0x07
Channel BA in functional mode without AIS-L
0x30098
0x07
Channel BB in functional mode without AIS-L
0x300B0
0x07
Channel BC in functional mode without AIS-L
0x300C8
0x07
Channel BD in functional mode without AIS-L
Table 5. Channel Alignment, Transparent TOH (Continued)
Register
Address
Value
Description
Initial Register Settings
PFU
FPGA
Logic
SONET
SERDES
register bits
bypass
8 - bit
8- bit
1- bit
SONET
SERDES
bypass
register bits
Alignment
FIFO
-FPGA_SYSCLK or CDR_CLK_xx
-FPGA_SYSCLK if alignment FIFO is used
8-bit
1- bit
register bit
Pointer
Mover /
DOUTxx[7:0]
FPGA_SYSCLK
DINxx[7:0]
System
Clock
RX Serial Data
TX Serial Data
I/O MUX, I/O DEMUX
And LVDS Buffers
PLL
PFU
8 - bit
8- bit
-Per channel CDR_CLK_xx if alignment FIFO is not used
8-bit
8 -bit
-
Interpreter
Receive (RX)
Path
Transmit (TX)
Path
Embedded
Core
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ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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