參數(shù)資料
型號(hào)： ORT8850L-3BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 63/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
60
3000C
[0:3]
R/W
number of consec-
utive A1 A2 errors
to generate [0:3]
00
If a particular channel’s “A1 A2 error insert command” control
bit is set to the value 1 then the “A1 and A2 error insert values”
will be inserted into that channels respective A1 and A2 bytes.
The number of consecutive frames to be corrupted is deter-
mined by the “number of consecutive A1 A2 errors to generate
[0:3]” control bits.
MSB is bit 3
[4]
R/W
backplane side
loopback control
0
0 = No loopback.
1 = RX to TX loopback on backplane side. Serial input is run
through SERDES and SONET block, then looped back in paral-
lel to SERDES and out serial.
[5]
R/W
DINxx/DOUTxx
parallel bus parity
control
1
0 = Odd parity
1 = Even parity
[6]
R/W
scram-
bler/descrambler
1
0 = no RX direction, descramble / TX direction scramble
1 = In RX direction, descramble channel after the SONET frame
recovery. In TX direction, scramble data just before parallel-to-
serial conversion
[7]
-
Not Used
0
3000D
[0:7]
R/W
A1 error insert
value [0:7]
00
Value of the A1 byte for error insert
3000E
[0:7]
R/W
A2 error insert
value [0:7]
00
Value of the A2 byte for error insert
3000F
[0:7]
R/W
transmit B1 error
insert mask [0:7]
00
0 = No error insertion.
1 = Invert corresponding bit in B1 byte.
30010
[0]
R
AA alarm
0
Consolidation alarm for channel AA
1 = alarm
0 = no alarm.
[1]
R
AB alarm
0
Consolidation alarm for channel AB
1 = alarm
0 = no alarm.
[2]
R
AC alarm
0
Consolidation alarm for channel AC
1 = alarm
0 = no alarm.
[3]
R
AD alarm
0
Consolidation alarm for channel AD
1 = alarm
0 = no alarm.
[4-7]
-
Not Used
0
30011
[0]
R/W
AA/BA alarm
enable/mask regis-
ter
0
AA and BA enable
1 = enabled
0 = not enabled
[1]
R/W
AB/BB alarm
enable/mask regis-
ter
0
AB and BB enable
1 = enabled
0 = not enabled
[2]
R/W
AC/BC alarm
enable/mask regis-
ter
0
AC and BC enable
1 = enabled
0 = not enabled
[3]
R/W
AD/BD alarm
enable/mask regis-
ter
0
AD and BD enable
1 = enabled
0 = not enabled
[4-7]
-
Not Used
0
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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參數(shù)描述
ORT8850L-3BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 278 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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