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MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-75
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip-select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type,
address, type of access, transfer size, and interrupt priority (in the case of interrupt
acknowledge) to parameters stored in chip-select registers. If all parameters match,
the appropriate chip-select signal is asserted. Chip-select signals are active low. If a
chip-select function is given the same address as a microcontroller module or an inter-
nal memory array, an access to that address goes to the module or array, and the chip-
select signal is not asserted. The external address and data buses do not reflect the
internal access.
All chip-select signals except CSBOOT are disabled after the release of RESET, and
cannot be asserted until the R/W[1:0] and BYTE[1:0] fields in the corresponding option
register are programmed to non-zero values. CSBOOT is automatically enabled out of
reset in 8-bit and 16-bit expanded modes. Alternate functions for chip-select pins are
enabled if appropriate data bus pins are held low at the release of RESET. Refer to
diagram of a single chip-select circuit.
Figure 4-22 Chip-Select Circuit Block Diagram
4.9.1 Chip-Select Pin Assignment Register
The pin assignment registers contain twelve 2-bit fields that determine the functions of
the chip-select pins. Each pin has two or three possible functions, as shown in Table CHIP SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
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Freescale Semiconductor, Inc.
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