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MC68F375
STATIC RANDOM ACCESS MEMORY (SRAM)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
11-6
11.4.1 Normal Operation
Normal operation is when the SRAM may be accessed via the IMB3 by a bus master
and is being powered by VDDL. The array may be accessed as byte or word. Access
may be either read or write.
11.4.1.1 Read/Write
The SRAM module allows a byte or aligned word read/write in one IMB3 bus cycle.
Long word read/write will require an additional bus cycle. An IMB3 bus cycle requires
2 system clocks.
11.4.2 Standby Operation
A separate supply pin is used by the standby SRAM module to maintain the contents
of the SRAM array during a power down phase. The external supply pin of the MCU is
known as VSTBY. Data in the standby SRAM will be retained down to the lowest supply
TICS. Circuitry within the standby SRAM module will automatically switch between
VDDL and VSTBY. The SRAM module will switch to standby power when VDDL < VSTBY
- VSWITCH.
When the SRAM array is powered by the VSTBY pin of the MCU, access to the SRAM
array is blocked. Data read from the SRAM array during this condition will not be valid.
Data written to the SRAM may be corrupted if switching occurs during a write opera-
tion. For the module to function correctly as general purpose SRAM, the maximum
value for VSTBY ≤ VDDL.
11.4.2.1 Power Down
In order to guarantee valid standby SRAM data during power down, external low volt-
age inhibit circuitry, (external to the MCU), must be designed to force the RESET pin
into the active state before VDDL drops below its normal limit. This is necessary to
inhibit a write cycle to the SRAM during power down.
11.4.3 RESET Operation
When a synchronous reset occurs, a bus master will be allowed, as a result of internal
synchronization, to complete the current access. Thus, a write bus cycle, byte or word,
that is in progress when a synchronous reset occurs will be completed without error.
During the RESET state, once an in-progress write has been completed, further writes
to the standby SRAM array will be inhibited.
Table 11-4 SRAM Array Read/Write Minimum Access Times
TYPE
Bus Cycles Required
for Read or Write
Number of System
Clocks
Byte
1
2
Aligned Word
1
2
Aligned Long Word
2
4
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Freescale Semiconductor, Inc.
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