MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-41
Table 5-14 QACR2 Bit Settings
Bit(s)
Name
Description
15
CIE2
Queue 2 completion interrupt enable. CIE2 enables completion interrupts for queue 2. The inter-
rupt request is generated when the conversion is complete for the last CCW in queue 2.
0 = Queue 2 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 2.
14
PIE2
Queue 2 pause interrupt enable. PIE2 enables pause interrupts for queue 2. The interrupt
request is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 2 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 2 which has the pause bit set.
13
SSE2
Queue 2 single-scan enable bit. SSE2 enables a single-scan of queue 2 after a trigger event
occurs. The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for
the single-scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE2 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 2. The QADC64 clears SSE2 when the single-scan is complete.
12:8
MQ2
Queue 2 operating mode. The MQ2 field selects the queue operating mode for queue 2. Table 5-15 shows the bits in the MQ2 field which enable different queue 2 operating modes.
7
RESUME
Queue 2 resume. RESUME selects the resumption point after queue 2 is suspended by queue
1. If RESUME is changed during execution of queue 2, the change is not recognized until an end-
of-queue condition is reached, or the queue operating mode of queue 2 is changed.
0 = After suspension, begin execution with the first CCW in queue 2 or the current subqueue.
1 = After suspension, begin execution with the aborted CCW in queue 2.
6:0
BQ2
Beginning of queue 2. The BQ2 field indicates the location in the CCW table where queue 2
begins. The BQ2 field also indicates the end-of-queue 1 and thus creates an end-of-queue con-
dition for queue 1. Setting BQ2 to any value
≥ 64 (1000000) allows the entire RAM space for
queue 1 CCW’s.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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