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MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-30
The output flip-flop is set when a match occurs on channel A. The output flip-flop is
reset when a match occurs on channel B. The polarity of the output signal is selected
by the EDPOL bit. The output flip-flop level can be obtained at any time by reading the
IN bit.
If subsequent enabled output compares occur on channels A and B, the output pulses
continue to be output, regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-
flop to the level corresponding to a comparison on channel A or B, respectively. Note
that the FLAG bit is not affected by these ‘force’ operations.
Totem pole or open-drain output circuit configurations can be selected using the WOR
bit in the DASMSIC register.
WARNING
There is no hardware protection to disable comparator B while com-
parator A is enabled. It is the user’s responsibility to load data
registers A and B with the values needed to produce the desired out-
put pulse.
NOTE
If both channels are loaded with the same value they will try to force
different levels on the output flip-flop. Hardware protection circuitry
ensures that no contention occurs and the output flip-flop provides a
logic zero level output.
Single Shot Output Pulse Operation — The single shot output pulse operation is
selected by writing the leading edge value of the desired pulse to data register A and
the trailing edge value to data register B. A single pulse will be output at the desired
time, thereby disabling the comparators until new values are written to the data regis-
ters. In this mode, registers A and B2 are accessible to the user software (at
consecutive addresses). Figure 13-10 provides an example of how the DASM can be
used to generate a single output pulse.
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Freescale Semiconductor, Inc.
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