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MC68F375
CDR MoneT FLASH FOR THE IMB3 (CMFI)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
10-29
Table 10-13 Program Interlock State Descriptions
State
Mode
Next
State
Transition Requirement
S1
Normal Operation:
Normal array reads and register accesses.
The Block protect information and pulse width tim-
ing control can be modified.
S2
T2
Write PE = 0, SES = 1
S2
First Program Hardware Interlock Write:
Normal read operation still occurs.
The array will accept programming writes
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 cannot change EHV at this
time.
If the write is to a register no data will be stored in
the program page buffers and the CMFI shall re-
main in state S2.
S1
T1
Write SES = 0 or master reset
S3
T3
Hardware Interlock
Write to any CMFI array location
This programming write will latch the
selected word of data into the pro-
gramming page buffer and the address
shall be latched to select the location
that will be programmed.
Once a bit has been written then it shall
remain in the program buffer until an-
other write to the word or a write of
SES = 0 or a program margin read de-
termines that the state of the bit needs
no further modification by the program
operation
If the write is to a register no data will
be stored in the program page buffers
and the CMFI shall remain in state S2
S3
Expanded Program Hardware Interlock Operation:
Program margin reads will occur.
Programming writes are accepted so that all pro-
gram pages may be programmed.
These writes may be to any CMFI array location.
The program page buffers will be updated using
only the data, the lower address (IADDR[5:2]) and
the block address.
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 can change EHV.
If the write is to a register no data will be stored in
the program page buffer.
S1
T6
Write SES = 0 or master reset
S4
T4
Write EHV = 1.
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Freescale Semiconductor, Inc.
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