- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1994 > DS3105LN+ (Maxim Integrated Products)IC TIMING LINE CARD 64-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 88/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁當(dāng)前第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
DS3105
66
Register Name:
ICR3, ICR4, ICR5, ICR6, ICR9
Register Description:
Input Configuration Register 3, 4, 5, 6, 9
Register Address:
22h, 23h, 24h, 25h, 28h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
Default
0
see below
Note: These registers are identical in function. ICRx is the control register for input clock ICx.
Bit 7: DIVN Mode (DIVN). When DIVN is set to 1 and LOCK8K = 0, the input clock is divided down by a
programmable predivider. The resulting output clock is then passed to the DPLL. All input clocks for which DIVN =
1 are divided by the factor specified in DIVN1 and DIVN2. When DIVN = 1 and LOCK8K = 0 in an ICR register, the
FREQ field of that register must be set to the input frequency divided by the divide factor. When DIVN = 1 and
LOCK8K = 1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See
0 = Disabled
1 = Enabled
Bit 6: LOCK8K Mode (LOCK8K). When LOCK8K is set to 1 and DIVN = 0, the input clock is divided down by a
preset predivider. The resulting output clock, which is always 8kHz, is then passed to the DPLL. LOCK8K is
ignored when DIVN = 0 and FREQ[3:0] = 1001 (2kHz) or 1010 (4kHz). When DIVN = 1 and LOCK8K = 1 in an ICR
register, the FREQ field of that register is decoded as the alternate frequencies. See Sections 7.4.2.2 and 7.4.2.3
0 = Disabled
1 = Enabled
Bits 5 and 4: Leaky Bucket Configuration (BUCKET[1:0]). Each input clock has leaky bucket accumulator logic
in its activity monitor. The LBxy registers at addresses 50h to 5Fh specify four different leaky bucket configurations.
Any of the four configurations can be specified for the input clock. See Section 7.5.2.
00 = Leaky bucket configuration 0
01 = Leaky bucket configuration 1
10 = Leaky bucket configuration 2
11 = Leaky bucket configuration 3
Bits 3 to 0: Input Clock Frequency (FREQ[3:0]). When DIVN = 0 and LOCK8K = 0 (standard direct-lock mode),
this field specifies the input clock’s nominal frequency for direct-lock operation. When DIVN = 0 and LOCK8K = 1
(LOCK8K mode) this field specifies the input clock’s nominal frequency for LOCK8K operation. When DIVN = 1 and
LOCK8K = 0 (DIVN mode), this field specifies the frequency after the DIVN divider (i.e., input frequency divided by
DIVN + 1). When DIVN = 1 and LOCK8K = 1 (alternate direct-lock frequencies), this field specifies the input clock’s
nominal frequency for direct-lock operation.
DIVN = 0 or LOCK8K = 0: (Standard direct-lock mode, LOCK8K mode, or DIVN mode)
0000 = 8kHz
0001 = 1544kHz or 2048kHz (as determined by SONSDH bit in the MCR3 register)
0010 = 6.48MHz
0011 = 19.44MHz
0100 = 25.92MHz
0101 = 38.88MHz
0110 = 51.84MHz
0111 = 77.76MHz
1000 = 155.52MHz (only valid for LVDS inputs)
1001 = 2kHz
1010 = 4kHz
1011 = 6312kHz
1100 = 5MHz
1101 = 31.25 MHz (not a multiple of 8 kHz and therefore not valid for LOCK8K mode)
1110–1111 = undefined
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3106LN+ | IC TIMING LINE CARD 64-LQFP |
| DS3231MZ+ | IC RTC I2C 8SOIC |
| DS3231SN#T&R | IC RTC W/TCXO 16-SOIC |
| DS3232MZ+ | IC RTC W/SRAM I2C 8SOIC |
| DS3232SN#T&R | IC RTC W/TCXO 20-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。