參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 54/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 160
類型： 定時卡 IC，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應商設備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
35
7.8
Output Clock Configuration
A total of four output clock pins, OC3, OC6, FSYNC, and MFSYNC, are available on the device. Output clocks OC3
and OC6 are individually configurable for a variety of frequencies. Output clocks FSYNC and MFSYNC are more
specialized, serving as an 8kHz frame sync (FSYNC) and a 2kHz multiframe sync (MFSYNC). Table 7-6 provides
more detail on the capabilities of the output clock pins.
Table 7-6. Output Clock Capabilities
OUTPUT
CLOCK
SIGNAL
FORMAT
FREQUENCIES SUPPORTED
OC3
CMOS/TTL
Frequency selection per Section 7.8.2.3 and Table 7-7 to Table 7-13.
OC6
LVDS/LVPECL
FSYNC
CMOS/TTL
8kHz frame sync with programmable pulse width and polarity.
MFSYNC
2kHz multiframe sync with programmable pulse width and polarity.
7.8.1 Signal Format Configuration
Output clock OC6 is an LVDS-compatible, LVPECL level-compatible outputs. The type of output can be selected or
the output can be disabled using the OC6SF configuration bits in the MCR8 register. The LVPECL level-compatible
mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers
have a limited common-mode signal range that can be accommodated for by using an AC-coupled signal. The
LVDS electrical specifications are listed in Table 10-5, and the recommended LVDS termination is shown in Figure
10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-6, and the recommended
LVPECL receiver termination is shown in Figure 10-3. These differential outputs can be easily interfaced to LVDS,
LVPECL, and CML inputs on neighboring ICs using a few external passive components. See App Note HFAN-1.0
for details.
Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2 Frequency Configuration
The frequency of output clocks OC3 and OC6 is a function of the settings used to configure the components of the
T0 and T4 PLL paths. These components are shown in the detailed block diagram of Figure 7-1.
The DS3105 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time, resulting in jitter with an amplitude typically less than 1ns pk-pk.
7.8.2.1 T0 and T4 DPLL Details
See Figure 7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to
synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single
DFS output clock signal, whereas there are two DFS output clock signals in the T0 DPLL—one for the output
clocks and one for the feedback clock.
In the T0 DPLL the feedback clock-signal output handles phase build-out or any phase offset configured in the
OFFSET registers. Thus the T0 DPLL output-clock signals and the feedback clock signal are frequency-locked but
may have a phase offset. The T0 and T4 feedback-DFS blocks are always connected to the T0 forward DFS and
the T4 forward DFS, respectively. The feedback DFS blocks synthesize the appropriate locking frequencies for use
by the phase-frequency detectors (PFDs). See Section 7.4.2.
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