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參數(shù)資料
| 型號： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 50/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 160 |
| 類型： | 定時卡 IC，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
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When USEMCPD = 1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In
this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the
dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is
used in the DPLL loop.
When the input clock is divided before being sent to the phase detector, the divider output clock edge gets aligned
to the feedback clock edge before the DPLL starts to lock to a new input clock signal or after the input clock signal
has a temporary signal loss. This helps ensure locking to the nearest input clock edge, which reduces output
transients and decreases lock times.
7.7.6 Loss-of-Lock Detection
Loss-of-lock can be triggered by any of the following in both the T0 and T4 DPLLs:
The fine phase-lock detector (measures phase between input and feedback clocks)
The coarse phase-lock detector (measures whole cycle slips)
Hard frequency limit detector
Inactivity detector
The fine phase-lock detector is enabled by setting FLEN = 1 in the PHLIM1 register. The fine phase limit is
configured in the FINELIM field of PHLIM1.
The coarse phase-lock detector is enabled by setting CLEN = 1 in the PHLIM2 register. The coarse phase limit is
configured in the COARSELIM field of PHLIM2. This coarse phase-lock detector is part of the multicycle phase
detector (MCPD) described in Section 7.7.5. The COARSELIM field sets both the MCPD range and the coarse
phase limit, since the two are equivalent. If loss-of-lock should not be declared for multiple-UI input jitter, the fine
phase-lock detector should be disabled and the coarse phase-lock detector should be used instead.
The hard frequency limit detector is enabled by setting FLLOL = 1 in the DLIMIT3 register. The hard limit for the T0
±80ppm. When the DPLL
frequency reaches the hard limit, loss-of-lock is declared. The DLIMIT3 register also has the SOFTLIM field to
specify a soft frequency limit. Exceeding the soft frequency limit does not cause loss-of-lock to be declared. When
the T0 DPLL frequency reaches the soft limit, the T0SOFT status bit is set in the OPSTATE register. When the T4
DPLL frequency reaches the soft limit, the T4SOFT status bit is set in OPSTATE.
The inactivity detector is enabled by setting NALOL = 1 in the PHLIM1 register. When this detector is enabled the
DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3.
When the T0 DPLL declares loss-of-lock, the state machine immediately transitions to the loss-of-lock state, which
sets the STATE bit in the MSR2 register and requests an interrupt if enabled.
When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the OPSTATE register, which sets the
T4LOCK bit in the MSR3 register and requests an interrupt if enabled.
7.7.7 Phase Build-Out
7.7.7.1 Automatic Phase Build-Out in Response to Reference Switching
When MCR10:PBOEN = 0, phase build-out is not performed during reference switching. The T0 DPLL always
locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to
the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients
on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference.
When MCR10:PBOEN = 1, phase build-out is performed during reference switching (or exiting from holdover). With
PBO enabled, if the selected reference fails and another valid reference is available, the device enters a temporary
holdover state in which the phase difference between the new reference and the output is measured and fed into
the DPLL loop to absorb the input phase difference. Similarly, during transitions from full-holdover, mini-holdover,
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相關代理商/技術參數(shù) |
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| DS3105LN+ | 功能描述:計時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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