參數(shù)資料
型號(hào): DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 34/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
17
Table 6-6. Power-Supply Pin Descriptions
PIN NAME
PIN DESCRIPTION
VDD
P
Core Power Supply. 1.8V
±10%.
VDDIO
P
I/O Power Supply. 3.3V
±5%.
VSS
P
Ground Reference
AVDD_DL
P
Power Supply for OC6 Digital Logic. 1.8V
±10%.
AVSS_DL
P
Return for OC6 Digital Logic
VDD_OC6
P
Power Supply for Differential Output OC6POS/NEG. 1.8V
±10%.
VSS_OC6
P
Return for LVDS Differential Output OC6POS/NEG
AVDD_PLL1
P
Power Supply for Master Clock Generator APLL. 1.8V
±10%.
AVSS_PLL1
P
Return for Master Clock Generator APLL
AVDD_PLL2
P
Power Supply for T0 APLL. 1.8V
±10%.
AVSS_PLL2
P
Return for T0 APLL
AVDD_PLL3
P
Power Supply for T4 APLL. 1.8V
±10%.
AVSS_PLL3
P
Return for T4 APLL
AVDD_PLL4
P
Power Supply for T0 APLL2. 1.8V
±10%.
AVSS_PLL4
P
Return for T0 APLL2
Note 1: All pin names with an overbar (e.g.,
RST) are active low.
Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description.
PIN TYPES
I = input pin
IDIFF = input pin that is LVDS/LVPECL differential signal compatible
IPD = input pin with internal 50k pulldown
IPU = input pin with internal 50k pullup
I/O = input/output pin
IOPD = input/output pin with internal 50k pulldown
IOPU = input/output pin with internal 50k pullup
O = output pin
O3 = output pin that can be placed in a high-impedance state
ODIFF = output pin that is LVDS/LVPECL differential signal compatible
P = power-supply pin
Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.
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