參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 7/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
104
9.
JTAG Test Access Port and Boundary Scan
9.1
JTAG Description
The DS3105 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. Figure 9-1 shows a block diagram. The DS3105 contains
the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture:
Test Access Port (TAP)
Bypass Register
TAP Controller
Boundary Scan Register
Instruction Register
Device Identification Register
The TAP has the necessary interface pins, namely JTCLK,
JTRST, JTDI, JTDO, and JTMS. Details on these pins
can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 9-1. JTAG Block Diagram
BOUNDARY SCAN
REGISTER
DEVICE
IDENTIFICATION
REGISTER
BYPASS REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
MUX
SELECT
THREE-STATE
JTDI
50k
JTMS
50k
JTCLK
JTRST
50k
JTDO
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