參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 84/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
62
Register Name:
VALSR1
Register Description:
Input Clock Valid Status Register 1
Register Address:
0Eh
Bit #
7
6
5
4
3
2
1
0
Name
IC6
IC5
IC4
IC3
Default
0
Bits 5 to 2: Input Clock Valid Status (IC[6:3]). Each of these real-time status bits is set to 1 when the
corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0, LOCK = 0 in the
corresponding ISR register). See also the MSR1 register and Section 7.5.
0 = Invalid
1 = Valid
Register Name:
VALSR2
Register Description:
Input Clock Valid Status Register 2
Register Address:
0Fh
Bit #
7
6
5
4
3
2
1
0
Name
HORDY
IC9
Default
0
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a
holdover value that has been averaged over the one-second holdover averaging period. See the related latched
status bit in MSR4 and Section 7.7.1.6.
Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in VALSR1 but for the IC9 clock.
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