參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 87/124頁
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
65
Register Name:
IPR2
Register Description:
Input Priority Register 2
Register Address:
19h
Bit #
7
6
5
4
3
2
1
0
Name
PRI4[3:0]
PRI3[3:0]
Default
0
1
0
1
0
Bits 7 to 4: Priority for Input Clock 4 (PRI4[3:0]). Priority 0001 is highest; priority 1111 is lowest. When
MCR11:T4T0 = 0, PRI4 configures IC4’s priority for the T0 DPLL. See Section 7.6.1. When PRI4 is written with a
value > 0, IPR3:PRI6 is forced to 0 (disabled).
0000 = IC4 unavailable for selection
0001–1111= IC4 relative priority
Bits 3 to 0: Priority for Input Clock 3 (PRI3[3:0]). Priority 0001 is highest; priority 1111 is lowest. When
MCR11:T4T0 = 0, PRI3 configures IC3’s priority for the T0 DPLL. See Section 7.6.1. When PRI3 is written with a
value > 0, IPR3:PRI5 is forced to 0 (disabled).
0000 = IC3 unavailable for selection
0001–1111= IC3 relative priority
Register Name:
IPR3
Register Description:
Input Priority Register 3
Register Address:
1Ah
Bit #
7
6
5
4
3
2
1
0
Name
PRI6[3:0]
PRI5[3:0]
Default
0
This register has the same behavior as IPR2 but for input clocks IC5 and IC6.
Register Name:
IPR5
Register Description:
Input Priority Register 5
Register Address:
1Ch
Bit #
7
6
5
4
3
2
1
0
Name
PRI9[3:0]
Default
0
1
0
This register has the same behavior as IPR2 but for input clock IC9.
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