參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 30/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
13
6.
Pin Descriptions
Table 6-1. Input Clock Pin Descriptions
PIN NAME
PIN DESCRIPTION
REFCLK
I
Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local
oscillator (XO or TCXO). See Section 7.3.
IC3
IPD
Input Clock 3. CMOS/TTL. Programmable frequency (default 8kHz). This input can be
associated with the SYNC1 pin.
IC4
IPD
Input Clock 4. CMOS/TTL. Programmable frequency (default 8kHz). This input can be
associated with the SYNC2 pin.
IC5POS,
IC5NEG
IDIFF
Input Clock 5. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44MHz).
CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS.
If not used these pins should be left unconnected (one input is internally pulled high and the
other internally pulled low). This input can be associated with the SYNC1 pin.
IC6POS,
IC6NEG
IDIFF
Input Clock 6. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).
CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS.
If not used these pins should be left unconnected (one input is internally pulled high and the
other internally pulled low). This input can be associated with the SYNC2 pin.
IC9
IPD
Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44MHz). This input can be
associated with the SYNC3 pin.
SYNC1
IPD
Frame-Sync 1 Input. 2kHz, 4kHz, or 8kHz.
FSCR3:SOURCE ! = 11XX. This pin is the external frame-sync input associated with any input
pin using the FSCR3:SOURCE field.
FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC3 or
IC5, depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].
SYNC2
IPD
Frame-Sync 2 Input. 2kHz, 4kHz, or 8kHz.
FSCR3:SOURCE ! = 11XX. This pin is not used for the external frame-sync signal.
FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC4 or
IC6, depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].
SYNC3/O3F0
IPU
Frame-Sync 3 Input/OC3 Frequency Select 0. 2kHz, 4kHz, or 8kHz. This pin is sampled
when the
RST pin goes high and the value is used as O3F0, which, together with O3F2 and
O3F1, sets the default frequency of the OC3 output clock pin. See Table 7-18. After
RST goes
high, this pin becomes the SYNC3 input pin (2kHz, 4kHz, or 8kHz) associated with IC9. It is
only used as SYNC3 when FSCR2.SOURCE = 11XX.
Table 6-2. Output Clock Pin Descriptions
PIN NAME
PIN DESCRIPTION
OC3
O
Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by
O3F[2:0] pins when the
RST pin goes high, 19.44MHz if O3F[2:0] pins left open.See Table
OC6POS,
OC6NEG
ODIFF
Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by
O6F[2:0] pins when the
RST pin goes high, 38.88MHz if O6F[2:0] pins left open. The output
mode is selected by MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure
FSYNC
O3
8kHz FSYNC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.8KINV and
FSCR1.8KPUL.
MFSYNC
O3
2kHz MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.2KINV and
FSCR1.2KPUL.
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