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參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 64/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
44
7.8.2.6 Custom Output Frequencies
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MHz and any multiple of 8kHz up to 311.04MHz. (An APLL must be used to achieve frequencies above
77.76MHz.) Any of the programmable output clocks can be configured to output the custom frequency or
submultiples thereof. Contact Microsemi timing products technical support for help with custom frequencies.
7.9
Frame and Multiframe Alignment
In addition to receiving and locking to clocks such as 19.44MHz from system timing cards, the DS3105 can also
receive and align its outputs to 2kHz multiframe-sync or 8kHz frame-sync signals from system timing cards. In this
mode of operation, both a higher speed clock (such as 6.48MHz or 19.44MHz) and a frame (or multiframe) sync
signal from each timing card are passed to the line cards. The higher speed clock from each timing card is
connected to a regular input clock pin on the DS3105, such as IC3 or IC4, while the associated frame-sync signal
is connected to a SYNCn input pin on the DS3105, such as SYNC1 or SYNC2. The DS3105 locks to the higher
speed clock from one of the timing cards and samples the associated frame-sync signal. The DS3105 then uses
the SYNCn signal to falling-edge align some or all the output clocks. When the SYNCn signal is a 2kHz clock,
output clocks 2kHz and above are falling-edge aligned. A 4kHz or 8kHz clock can also be used on the SYNCn pins
without any changes to the register configuration, but only output clocks of 8kHz and above are aligned in this
case. Only the falling edge of the SYNCn signal has significance. Phase build-out should be disabled (PBOEN = 0
in MCR10) when using SYNCn signals.
An external frame sync signal is only allowed to align output clocks if the T0 DPLL is locked and the SYNCn signal
7.9.1 Enable and SYNCn Pin Selection
Table 7-19 shows how to configure the device for various external frame-sync modes. When MCR3:EFSEN = 0,
external frame sync is disabled. When EFSEN = 1, three different external frame-sync modes are available:
SYNC1 Manual, SYNC1 Auto, and SYNC123.
In SYNC1 Manual mode, external frame sync is enabled on the SYNC1 pin whenever the T0 DPLL is locked,
regardless of which input clock is the selected reference. When the T0 DPLL is not locked, external frame sync is
disabled. In this mode the SYNC2 and SYNC3 pins are ignored.
In SYNC1 Auto mode, external frame sync is automatically enabled on the SYNC1 pin when the T0 DPLL is locked
to the input clock pin specified by FSCR3:SOURCE. If the T0 DPLL is not locked or is locked to a different input
clock than the one specified by the SOURCE field, then external frame sync is disabled. In this mode the SYNC2
and SYNC3 pins are ignored.
In SYNC123 mode, the SYNC1, SYNC2, and SYNC3 pins are each associated with one or more input clock pins
as specified by FSCR1:SYNCSRC. SYNC1 can be associated with IC3 or IC5 or both. SYNC2 can be associated
with IC4 or IC6 or both. SYNC3 is always associated with IC9. When the T0 DPLL is locked to one of the input
clock pins associated with a SYNCn pin, external frame sync is automatically enabled with the corresponding
SYNCn pin as the source. When the T0 DPLL is not locked or is locked to an input clock pin that is not associated
with a SYNCn pin then external frame sync is disabled.
Since SYNC123 mode is always automatic, MCR3:AEFSEN takes on a different meaning in this mode, specifying
whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
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| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
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