參數(shù)資料
型號： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 4/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
101
Register Name:
FSCR2
Register Description:
Frame-Sync Configuration Register 2
Register Address:
7Bh
Bit #
7
6
5
4
3
2
1
0
Name
INDEP
OCN
PHASE3[1:0]
PHASE2[1:0]
PHASE1[1:0]
Default
0
Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). When this bit is set to 0, the 8kHz frame sync on
FSYNC and the 2kHz multiframe sync on MFSYNC are aligned with the other output clocks when synchronized
with the SYNCn input. When this bit is 1, the frame sync and multiframe sync are independent of the other output
clocks, and their edge position may change without disturbing the other output clocks. See Section 7.9.5.
0 = FSYNC and MFSYNC are aligned with other output clocks; all are synchronized by the SYNCn input.
1 = FSYNC and MFSYNC are independent of the other clock outputs; only FSYNC and MFSYNC are
synchronized by the SYNCn input.
Bit 6: Sync OC-N Rates (OCN). See Section 7.9.3.
0 = SYNCn is sampled with a 6.48MHz resolution; the selected reference must be 6.48MHz.
1 = If the selected reference is 19.44MHz, SYNCn is sampled at 19.44MHz. If the selected reference is
38.88MHz, SYNCn is sampled at 38.88MHz. The selected reference must be either 19.44MHz or
38.88MHz.
Bits 5 and 4: External Sync-Sampling Phase 3 (PHASE3[1:0]). This field adjusts the sampling of the SYNC3
input pin. Normally the falling edge of SYNC3 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
Bits 3 and 2: External Sync-Sampling Phase 2 (PHASE2[1:0]). This field adjusts the sampling of the SYNC2
input pin. Normally the falling edge of SYNC2 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
Bits 1 and 0: External Sync-Sampling Phase 1 (PHASE1[1:0]). This field adjusts the sampling of the SYNC1
input pin. Normally the falling edge of SYNC1 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
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參數(shù)描述
DS3105LN+ 功能描述:計(jì)時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel
DS3106 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC
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DS3106A14S2S 制造商:Amphenol Corporation 功能描述:
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