參數(shù)資料
型號(hào)： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 66/124頁
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
46
generators free-run with their existing 2kHz alignments. When the external frame sync is enabled and the SYNCn
signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by the SYNCn signal,
and, therefore, FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP = 0, the
T0 DPLL 2kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2kHz alignment generator to
falling-edge align all T0-derived output clocks with the SYNCn signal. When INDEP = 1, the T0 DPLL 2-kHz
alignment generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to
free-run with its existing 2kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when
the SYNCn signal has a change of phase position.
7.9.6 Frame-Sync Monitor
The frame-sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable
bit (MCR3:EFSEN).
When EFSEN = 1 (external frame sync enabled), the OPSTATE:FSMON bit is set when the SYNCn signal is not
qualified and cleared when SYNCn is qualified. If the SYNCn signal is disqualified, both 2kHz alignment generators
are immediately disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When
OPSTATE:FSMON is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled
in the IER3 register. If SYNCn immediately stabilizes at a new phase and proper frequency, it is requalified after 64
2kHz cycles (nominally 32ms). Unless system software intervenes, after the SYNCn signal is requalified the 2kHz
alignment generators will synchronize with SYNCn’s new phase alignment, causing a sudden phase movement on
the output clocks. System software can avoid this sudden phase movement on the output clocks by responding to
the FSMON interrupt within the 32ms window with appropriate action, which might include disabling external frame
sync (MCR3:EFSEN = 0) to prevent the resynchronization of the 2kHz alignment generators with SYNCn, forcing
the T0 DPLL into holdover (MCR1:T0STATE = 010) to avoid affecting the output clocks with any other phase hits,
and possibly even disabling the master timing card and promoting the slave timing card to master since the 2kHz
signal from the master should not have such phase movements.
When EFSEN = 0 (external frame sync disabled), OPSTATE:FSMON is set when the negative edge of the
resampled SYNCn signal is outside the window determined by FSCR3:MONLIM relative to the MFSYNC negative
edge (or positive edge if MFSYNC is inverted) and clear when within the window. When OPSTATE:FSMON is set,
the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the IER3 register.
7.9.7 Other Configuration Options
FSYNC and MFSYNC are always produced from the T0 DPLL. The other output clocks can also be configured as
2kHz or 8kHz outputs, derived from the T0 DPLL.
7.10 Microprocessor Interface
The DS3105 presents an SPI interface on the
CS, SCLK, SDI, and SDO pins. SPI is a widely used master/slave
bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. The
DS3105 is always a slave device. Masters are typically microprocessors, ASICs, or FPGAs. Data transfers are
always initiated by the master device, which also generates the SCLK signal. The DS3105 receives serial data on
the SDI pin and transmits serial data on the SDO pin. SDO is high impedance except when the DS3105 is
transmitting data to the bus master.
Bit Order. When both bit 3 and bit 4 are low at device address 3FFFh, the register address and all data bytes are
transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the
register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and
Motorola SPI convention is MSB first.
Clock Polarity and Phase. When CPOL = 0, SCLK is normally low and pulses high during bus transactions. The
CPHA pin sets the phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on the leading edge of
the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the
trailing edge of the SCLK pulse and updated on SDO on the following leading edge. SCLK does not have to toggle
between accesses, i.e., when
CS is high. See Figure 7-4.
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