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參數(shù)資料
| 型號： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 49/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
30
7.7.4 Damping Factor
The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping
factor of the T4 DPLL is configured in the DAMP field of the T4CR2 register. The reset default damping factors for
both DPLLs are chosen to give a maximum jitter/wander gain peak of approximately 0.1dB. Available settings are a
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
BANDWIDTH
(Hz)
DAMP[2:0]
VALUE
DAMPING
FACTOR
GAIN PEAK
(dB)
18
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
35
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4, 5
10
0.06
70 to 400
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4
10
0.06
5
20
0.03
7.7.5 Phase Detectors
Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are
available in the T0 and T4 DPLLs:
Phase/frequency detector (PFD)
Early/late phase detector (PD2) for fine resolution
Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times
These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As
with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle
phase detector detects and remembers phase differences of many cycles (up to 8191UI). When locking to 8kHz or
lower, the normal phase/frequency detectors are always used.
The T0 DPLL phase detectors can be configured for normal phase/frequency locking (
±360° capture) or nearest
edge phase locking (
±180° capture). With nearest edge detection the phase detectors are immune to occasional
missing clock cycles. The DPLL automatically switches to nearest edge locking when the multicycle phase detector
is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the
TEST1 register disables nearest edge locking and forces the T0 DPLL to use phase/frequency locking. The T4
DPLL always has nearest edge locking enabled.
The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2 fields of
registers T0CR2 and T0CR3 for the T0 DPLL and registers T4CR2 and T4CR3 for the T4 DPLL. The reset default
settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot
and bandwidth.
The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the
MCPD—from
±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase
position over many clock cycles, giving high jitter tolerance. Thus, the use of the MCPD is an alternative to the use
of LOCK8K mode for jitter tolerance. When a DPLL is direct locking to 8kHz, 4kHz, or 2kHz, or in LOCK8K mode,
the multicycle phase detector is automatically disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS3105LN+ | 功能描述:計時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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