REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC B23 STS1TXA_1_D0 TXHDLCDAT_1_0 TXGFCMSB_1 I/O TTL/ CMOS Transmit STS-1 T" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 81/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
51
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
B23
STS1TXA_1_D0
TXHDLCDAT_1_0
TXGFCMSB_1
I/O
TTL/
CMOS
Transmit STS-1 Telecom Bus Interface - Channel 1 - Input Data Bus
pin number 0/Transmit High-Speed HDLC Controller Input Interface
block - Channel 1 - Input Data Bus - Pin 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 1 is enabled.
If STS-1 Telecom Bus (Channel 1) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 0 -
STS1TXA_1_D0:
This input pin along with STS1TXA_1_D[7:1] functions as the Transmit
(Add) STS-1 Telecom Bus Interface - Input Data Bus for Channel 1. This
particular input pin functions as the LSB (Least Significant Bit) input pin
on the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus.
The Transmit STS-1 Telecom Bus Interface will sample and latch this pin
upon the falling edge of STS1TXA_CLK_1.
The LSB of any byte, which is being input into the STS-1 Transmit Tele-
com Bus Interface - Data Bus (for Channel 1) should be input via this
pin.
If the STS-1 Telecom Bus (associated with Channel 1) has been dis-
abled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - - Transmit High-Speed
HDLC Controller Input Interface block - Data Bus Input Pin # 0 -
Channel 1 - TxHDLCDAT_1_0:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 0 (the
LSB) within the Transmit High-Speed HDLC Controller Input Interface
block - Input Data Bus (e.g., the TxHDLCDat_1[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_1). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_1[7:0] input pins) upon the rising edge of the TxHDLCClk_1
clock output signal.
TXGFCMSB_1 (Transmit GFC MSB Indicator - Channel 1)
This input pin will only function in this role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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