REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC AC18 PRD_L/DS*/WE* I TTL READ Strobe /Data Strobe: The function of this i" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 79/133頁
文件大小： 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
5
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AC18
PRD_L/DS*/WE*
I
TTL
READ Strobe /Data Strobe:
The function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - RD* - READ Strobe Input:
If the Microprocessor Interface is operating in the Intel-Asynchronous
Mode, then this input pin will function as the RD* (Active "Low" READ
Strobe) input signal from the Microprocessor. Once this active-low sig-
nal is asserted, then the XRT94L31 will place the contents of the
addressed register (or buffer location) on the Microprocessor Bi-direc-
tional Data Bus (D[7:0]). When this signal is negated, the Data Bus will
be tri-stated.
Motorola-Asynchronous (68K) Mode - DS* - Data Strobe Input:
If the Microprocessor Interface is operating in the Motorola Asynchro-
nous Mode, then this input will function as the DS* (Data Strobe) input
signal.
PowerPC 403 Mode - WE* - Write Enable Input:
If the Microprocessor Interface is operating in the PowerPC 403 Mode,
then this input pin will function as the WE* (Write Enable) input pin.
Anytime the Microprocessor Interface samples this active-low input sig-
nal (along with CS* and WR*/R/W*) also being asserted (at a logic level)
upon the rising edge of PCLK, then the Microprocessor Interface will
(upon the very same rising edge of PCLK) latch the contents on the Bi-
Directional Data Bus (D[7:0]) into the target on-chip register or buffer
location within the XRT94L31.
AG23
ALE/AS_L
I
TTL
Address Latch Enable/Address Strobe:T
he function of this input pin depends upon which mode the Microproces-
sor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - ALE
If the Microprocessor Interface (of the XRT94L31) has been configured
to operate in the Intel-Asynchronous Mode, then this active-high input
pin is used to latch the address (present at the Microprocessor Interface
Address Bus input pins (A[14:0]) into the XRT94L31 Microprocessor
Interface block and to indicate the start of a READ or WRITE cycle. Pull-
ing this input pin "High" enables the input bus drivers for the Address
Bus input pins (A[14:0]). The contents of the Address Bus will be latched
into the XRT94L31 Microprocessor Interface circuitry, upon the falling
edge of this input signal.
Motorola-Asynchronous (68K) Mode - AS*
If the Microprocessor Interface has been configured to operate in the
Motorola-Asynchronous Mode, then this active-low input pin is used to
latch the data (residing on the Address Bus, A[14:0]) into the Micropro-
cessor Interface circuitry of the XRT94L31.
Pulling this input pin "Low" enables the input bus drivers for the Address
Bus input pins. The contents of the Address Bus will be latched into the
Microprocessor Interface circuitry, upon the rising edge of this signal.
PowerPC 403 Mode - No Function - Tie to GND:
If the MIcroprocessor Interface has been configured to operate in the
PowerPC 403 Mode, then this input pin has no role nor function and
should be tied to GND.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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