REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC AF6A D10A E10 RxPOHFrame_0 RxPOHFrame_1 RxPOHFrame_2 O CMOS Receive SONE" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 120/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
87
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AF6A
D10A
E10
RxPOHFrame_0
RxPOHFrame_1
RxPOHFrame_2
O
CMOS
Receive SONET POH Processor Block - Path Overhead Output Port
- Frame Boundary Indicator:
These output pins, along with the RxPOH_n, RxPOHClk_n and
RxPOHValid_n output pins function as the Receive SONET POH Pro-
cessor Block - Path Overhead Output Port.
These output pins will pulse "High" coincident with the very first POH
byte (J1), of a given STS-1 frame, is being output via the corresponding
RxPOH_n output pin.
AC10
AF7A
C11
RxPOHValid_0
RxPOHValid_1
RxPOHValid_2
O
CMOS
Receive SONET POH Processor Block - Path Overhead Output Port
- Valid POH Data Indicator:
These output pins, along with RxPOH_n, RxPOHClk_n and
RxPOHFrame_n function as the Receive SONET POH Processor block
- Path Overhead Output port.
These output pins will toggle "High" coincident with when valid POH data
is being output via the RxPOH_n output pins. This output is updated
upon the falling edge of RxPOHClk_n. Hence, external circuitry should
sample these signals upon rising edge of RxPOHClk_n.
AD11
LOF
O
CMOS
Receive STS-3 LOF (Loss of Frame) Indicator:
This output pin indicates whether or not the Receive STS-3 TOH Proces-
sor block (within the device) is currently declaring the LOF defect condi-
tion as described below.
"Low" - Indicates that the Receive STS-3 TOH Processor block is NOT
currently declaring the LOF defect condition.
"High" - Indicates that the Receive STS-3 TOH Processor block is cur-
rently declaring the LOF defect condition.
AF9
SEF
O
CMOS
Receive STS-3 SEF (Severed Errored Frame) Indicator:
This output pin indicates whether or not the Receive STS-3 TOH Proces-
sor block (within the device) is currently declaring the SEF defect condi-
tion as described below.
"Low" - Indicates that the Receive STS-3 TOH Processor block is NOT
currently declaring the SEF defect condition.
"High" - Indicates that the Receive STS-3 TOH Processor block is cur-
rently declaring the SEF defect condition.
AG7
LOS
O
CMOS
Receive STS-3 LOS (Loss of Signal) Defect Declared Indicator:
This output pin indicates whether or not the Receive STS-3 TOH Proces-
sor block (within the device) is currently declaring the LOS defect condi-
tion as described below.
"Low" - Indicates that the Receive STS-3 TOH Processor block is NOT
currently declaring the LOS defect condition.
"High" - Indicates that the Receive STS-3 TOH Processor block is cur-
rently declaring the LOS defect condition.
GENERAL PURPOSE INPUT/OUTPUT
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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