REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC F7 REFCLK45 I TTL DS3 Reference Clock Input for the Jitter Attenuator wi" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 122/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
89
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
F7
REFCLK45
I
TTL
DS3 Reference Clock Input for the Jitter Attenuator within the DS3/
E3 Mapper Block:
To operate any of the channels of the XRT94L31 in the DS3 Mode, apply
a clock signal with a frequency of 44.736±20ppm to this input pin.
This input pin functions as the timing reference for the DS3/E3/STS-1 Jit-
ter Attenuator (within the DS3/E3 Mapper block) for DS3 applications.
For DS3 Applications, the DS3/E3 Framer block will use this input clock
signal, as a timing source in order to transmit the DS3 AIS Pattern, in the
Egress Direction (e.g., from the XRT94L31 to the DS3/E3/STS-1 LIU
IC).
If the user does not intend to operate any of the three (3) channels in the
DS3 Mode, or if the user intends to configure the XRT94L31 to operate
in the SFM Mode, connect this input pin to GND.
BOUNDARY SCAN
F5
TDO
O
CMOS
Test Data Out: Boundary Scan Test data output
F4
TDI
I
TTL
TEST Data In: Boundary Scan Test data input:
NOTE: This input pin should be pulled "Low" for normal operation.
D3
TRST
I
TTL
JTAG Test Reset Input
E4
TCK
I
TTL
Test clock: Boundary Scan clock inputNote:
NOTE: This input pin should be pulled "Low" for normal operation.
E5
TMS
I
TTL
Test Mode Select: Boundary Scan Mode Select inputNote:
NOTE: This input pin should be pulled "Low" for normal operation.
FILTERING CAPACITORS
U6
RXCAPP
I
ANA-
LOG
External Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor, which is
used to minimize jitter peaking.
U5
RXCAPN
I
ANA-
LOG
External Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor, which is
used to minimize jitter peaking.
W6
RXCAPP_R
I
ANAL0
OG
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the positive side of the external capacitor, which is
used to minimize jitter peaking.
W5
RXCAPN_R
I
ANA-
LOG
External Redundant Loop Capacitor for Receive PLL:
This pin connects to the negative side of the external capacitor, which is
used to minimize jitter peaking.
MISCELLANEOUS PINS
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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