REV. 1.0.1 E9 TxE1F1E2Enable O CMOS Transmit E1-F1-E2 Byte Input Port - Enable (or " />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 51/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標準包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
24
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
E9
TxE1F1E2Enable
O
CMOS
Transmit E1-F1-E2 Byte Input Port - Enable (or Ready) Indicator
Output pin:
This output pin, along with the TxTOHClk output pin and the TxE1F1E2
input pin is used to insert their value for the E1, F1 and E2 bytes, into the
Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH Pro-
cessor block will accept this data and will insert into the E1, F1 and E2
byte-fields, within the outbound STS-3 data-stream.
Whatever external circuitry (which is connected to the TxTOHClk, the
TxE1F1E2 and this output pin), is suppose to do the following.
It should continuously monitor the state of this output pin.
Whenever this output pin pulses "High", then the external circuitry
should place the next orderwire bit (to be inserted into the Transmit STS-
3 TOH Processor block) onto the TxE1F1E2 input pin, upon the rising
edge of TxTOHClk.
Any data that is placed on the TxE1F1E2 input pin, will be sampled upon
the falling edge of TxOHClk.
C6
TxE1F1E2Frame
O
CMOS
Transmit E1-F1-E2 Byte Input Port - Framing Output Pin.
This output pin pulses "High" for one period of TxTOHClk, one TxTO-
HClk bit-period prior to the Transmit E1-F1-E2 Byte Input Port expecting
the very first byte of the E1 byte, within a given outbound STS-3 frame.
A4
TxE1F1E2
I
TTL
Transmit E1-F1-E2 Byte Input Port - Input Pin:
This input pin, along with the TxE1F1E2Enable and the TxTOHClk out-
put pins are used to insert their value for the E1, F1 and E2 bytes, into
the Transmit STS-3 TOH Processor Block. The Transmit STS-3 TOH
Processor block will accept this data and insert it into the E1, F1 and E2
byte fields, within the outbound STS-3 data-stream.
Whatever external circuitry that is interfaced to this input pin, the
TxE1F1E2Enable and the TxTOHClk pins is suppose to do the following.
It should continuously monitor the state of the TxE1F1E2Enable input
pin.
Whenever the TxE1F1E2Enable input pin pulses "High", then the exter-
nal circuitry should place the next orderwire bit (to be inserted into the
Transmit STS-3 TOH Processor block) onto this input pin upon the rising
edge of TxTOHClk.
Any data that is placed on the TxE1F1E2 input pin, will be sampled upon
the falling edge of TxTOHClk.Note:
NOTE: This pin should be connected to GND if it is not used.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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