REV. 1.0.1 AD20 AC19 AE22 AG24 AE21 AD19 AF23 AE20 PDATA_0 PDATA_1 PDATA_2 PDATA_3 P" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 68/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
4
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
AD20
AC19
AE22
AG24
AE21
AD19
AF23
AE20
PDATA_0
PDATA_1
PDATA_2
PDATA_3
PDATA_4
PDATA_5
PDATA_6
PDATA_7
I/O
TTL
Bi-Directional Data Bus pins (Microprocessor Interface):
These pins are used to drive and receive data over the bi-directional
data bus, whenever the Microprocessor performs READ and WRITE
operations with the Microprocessor Interface of the XRT94L31.
AF22
PWR_L/R/W*
I
TTL
Write Strobe/Read-Write Operation Identifier:
The function of this input pin depends upon which mode the Micropro-
cessor Interface has been configured to operate in, as described below.
Intel-Asynchronous Mode - WR* - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the Intel-Asyn-
chronous Mode, then this input pin functions as the WR* (Active-Low
WRITE Strobe) input signal from the Microprocessor. Once this active-
low signal is asserted, then the input buffers (associated with the Bi-
Directional Data Bus pins, D[7:0]) will be enabled. The Microprocessor
Interface will latch the contents on the Bi-Directional Data Bus (into the
target register or address location, within the XRT94L31) upon the rising
of this input.
Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identi-
fication Input Pin:
If the Microprocessor Interface is operating in the Motorola-Asynchro-
nous Mode, then this pin is functionally equivalent to the R/W* input pin.
In the Motorola Mode, a READ operation occurs if this pin is held at a
logic 1, coincident to a falling edge of the RD/DS* (Data Strobe) input
pin.
PowerPC 403 Mode - R/W* - Read/Write Operation Identification
Input:
If the Microprocessor Interface is configured to operate in the PowerPC
403 Mode, then this input pin will function as the Read/Write Operation
Identification input pin.
Anytime the Microprocessor Interface samples this input signal at a logic
"Low" (while also sampling the CS* input pin "Low") upon the rising edge
of PCLK, then the Microprocessor Interface will (upon the very same ris-
ing edge of PCLK) latch the contents of the Address Bus (A]14:0]) into
the Microprocessor Interface circuitry, in preparation for this forthcoming
READ operation. At some point (later in this READ operation) the Micro-
processor will also assert the DBEN*/OE* input pin, and the Micropro-
cessor Interface will then place the contents of the target register (or
address location within the XRT94L31) upon the Bi-Directional Dat Bus
pins (D[7:0]), where it can be read by the Microprocessor.
Anytime the Microprocessor Interface samples this input signal at a logic
"High" (while also sampling the CS* input pin at a logic "Low") upon the
rising edge of PCLK, then the Microprocessor Interface will (upon the
very same rising edge of PCLK) latch the contents of the Address Bus
(A[14:0]) into the Microprocessor Interface circuitry, in preparation for the
forthcoming WRITE operation. At some point (later in this WRITE oper-
ation) the Microprocessor will also assert the RD*/DS*/WE* input pin,
and the Microprocessor Interface will then latch the contents of the Bi-
Directional Data Bus (D[7:0]) into the contents of the target register or
buffer location (within the XRT94L31).
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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