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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 69/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
40
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
A13
D19
AF15
STS1TXA_ALARM_n
RXDS3NEG_n
RxLCV_n
STS1TXA_ALARM_n
RXDS3NEG_n
RxLCV_n
STS1TXA_ALARM_n
RXDS3NEG_n
RxLCV_n
I
TTL
Transmit STS-1 Telecom Bus - Alarm Indicator Input - Channel n/
Receive DS3/E3 Negative-Polarity Data Input from LIU - Channel n/
Receive DS3/E3 Line Code Violation Input from LIU - Channel n:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface for Channel n has been enabled.
If STS-1 Telecom Bus Interface (associated with Channel n) has
been enabled - Transmit STS-1 Telecom Bus Interface - Alarm Indi-
cator Input - STS1TxA_ALARM_n:
This input pin should be pulsed "High" for one STS1TxA_CLK_n period
coincident to whenever the Transmit STS-1 Telecom Bus Interface
(associated with Channel n) is accepting a byte from an incoming STS-1/
STS-3/STM-1 signal (via the STS1TxA_D_n[7:0] input pins) that is carry-
ing the AIS-P indicator.This input pin should be held at a logic "Low" at
all other times.
NOTE: If the STS1TXA_ALARM_n input signal pulses "High" for any
given STS-1 signal (within the incoming STS-1), then the
XRT94L31 will automatically declare the AIS-P defect condition
for that particular STS-1 channel.
If STS-1 Telecom Bus (Channel n) has NOT been enabled:
If the STS-1 Telecom Bus (Channel n) has NOT been enabled, then the
role that this particular input pin plays depends upon whether Channel n
is operating in the STS-1 Mode, the DS3/E3 Single-Rail Mode or in the
DS3/E3 Dual-Rail Mode, as described below.
If Channel n is operating in the STS-1 Mode - NO FUNCTION:
If Channel n is operating in the STS-1 Mode, then the user should tie this
pin to GND.
If Channel n is operating in the DS3/E3 Single-Rail Mode - Receive
LCV Input from LIU
If Channel n is operating in both the DS3/E3 and Single-Rail Modes,
then this input pin will function as the LCV (Line Code Violation) input
signal. In this mode, the user is expected to connect the LCV output pin
from the LIU IC to this input pin. The DS3/E3 Framer block will sample
this input pin upon the user-configured edge of the RXDS3LINECLK_n
clock signal, and the Primary Frame Synchronizer block (corresponding
with Channel n) will increment the PMON LCV or EXZ Event Count reg-
isters based upon the data sampled at this input pin.
If Channel n is operating in the DS3/E3 Dual-Rail Mode - Receive
DS3/E3 Negative-Polarity Data Input from LIU
If the user has configured Channel n to operate in both the DS3/E3 and
the Dual-Rail Mode, then only the negative-polarity portion of the
Receive DS3/E3 data output (from the DS3/E3 LIU IC) should be applied
to this input pin.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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