REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC NOTE:" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 17/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
113
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
NOTE: The value for t11 is presented in
Tables 15, 16, 17.and 18
1.3.7
Egress Timing for DS3/E3 Applications
Table 15 presents information on the Timing Parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Egress Direction) for DS3/E3 Applications and when the DS3/E3 Framer block has been configured to output
the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/STS_1_NEG_OUT signal upon
the rising edge of DS3/E3/STS_1_CLOCK_OUT.
Table 16 presents information on the Timing Parameters for the DS3/E3/STS-1 LIU Interface Signal (in the
Egress Direction) for DS3/E3 Applications and when the DS3/E3 Framer block has been configured to output
the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/STS_1_NEG_OUT signals upon
the falling edge of DS3/E3/STS_1_CLOCK_OUT.
1.3.8
Egress Timing for STS-1/STM-0 Applications
Table 17 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Egress Direction) for STS-1/STM-0 Applications and when the Transmit STS-1 TOH Processor block has been
configured to output the DS3/E3/STS_1_DATA_OUT signal upon the rising edge of DS3/E3/
STS_1_CLOCK_OUT.
FIGURE 17. AN ILLUSTRATION OF THE WAVEFORMS OF THE DS3/E3/STS-1 SIGNALS THAT ARE OUTPUT FROM THE
DS3/E3/STS-1 LIU INTERFACE (IN THE RECEIVE/EGRESS DIRECTION)
TABLE 15: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR DS3/E3
APPLICATIONS(RISING EDGE OF DS3/E3/STS_1_CLOCK_OUT)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t11
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
& DS3/E3/STS_1_NEG_OUT output delay
2.1ns
7.8ns
TABLE 16: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR DS3/E3
APPLICATIONS(FALLING EDGE OF DS3/E3/STS_1_CLOCK_OUT)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t11
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
& DS3/E3/STS_1_NEG_OUT output delay
1.6ns
6.5ns
DS3/E3/STS_1_DATA_OUT
DS3/E3/STS_1_CLOCK_OUT
DS3/E3/STS_1_NEG_OUT
t11
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