REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC P1 REFTTL I TTL 19.44MHz or 77.76MHz Clock Synthesizer Reference Clock I" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 13/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
11
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
P1
REFTTL
I
TTL
19.44MHz or 77.76MHz Clock Synthesizer Reference Clock Input
Pin:
The function of this input pin depends upon whether or not the Clock
Synthesizer block is enabled.
If Clock Synthesizer is Enabled.
If the Clock Synthesizer block is enabled, then it will be used to generate
the 155.52MHz, 19.44MHz and/or 77.76MHz clock signal for the Trans-
mit STS-3/STM-1 circuitry. In this mode, the user should apply a clock
signal of any of the following frequencies to this input pin.
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Afterwards, the user needs to write the appropriate data into the Trans-
mit Line Interface Control Register (Address Location = 0x0383) in order
to (1) configure the Clock Synthesizer Block to accept any of the above-
mentioned signals and generate a 155.52MHz, 19.44MHz or 77.76MHz
clock signal, (2) to configure the Clock Synthesizer to function as the
Clock Source for the STS-3/STM-1 block.
If Clock Synthesizer is NOT Enabled:
If the Clock Synthesizer block is NOT enabled, then it will NOT be used
to generate the 19.44MHz and/or 77.76MHz clock signal, for the STS-3/
STM-1 block. In this configuration seting, the user MUST apply a
19.44MHz clock signal to this input pin.
NOTE: The user must place a clock signal to this input pin in order to
perform READ and WRITE operations to much of the SONET/
SDH-related registers via the Microprocessor Interface.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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