REV. 1.0.1 C13 STS1TXA_0_D1 TXHDLCDAT_0_1 TXGFC_0 I TTL Transmit STS-1 Telecom Bus " />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 71/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
42
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
C13
STS1TXA_0_D1
TXHDLCDAT_0_1
TXGFC_0
I
TTL
Transmit STS-1 Telecom Bus Interface - Channel 0 - Data Bus Input
pin number 1/Transmit High-Speed HDLC Controller Input Interface
block - Channel 0 - Input Data Bus - Pin 1:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 0 is enabled.
If STS-1 Telecom Bus (Channel 0) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 1 -
STS1TxA_0_D1:
This input pin along with STS1TXA_0_D[7:2] and STS1TXA_0_D0 func-
tion as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data Bus
for Channel 0. The Transmit STS-1 Telecom Bus interface will sample
and latch this pin upon the falling edge of STS1TXA_CLK_0.
If the STS-1 Telecom Bus Interface (associated with Channel 0) has
been disabled:
This input pin can function in either of the following roles, depending
upon which mode the XRT94L31 has been configured to operate in, as
described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed
HDLC Controller Input Interface block - Channel 0 - Data Bus Input
pin # 1 - TxHDLCDAT_0_1:
If the XRT94L31 is configured to operate in the High-Speed HDLC Con-
troller over DS3/STS-3 Mode, then this input pin will function as Bit 1
within the Transmit High-Speed HDLC Controller Input Interface block -
Input Data Bus (e.g., the TxHDLCDat_0[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0). The
Transmit High-Speed HDLC Controller Input Interface block will sample
the data residing on this input pin (along with the rest of the
TxHDLCDat_0[7:0] input pins) upon the rising edge of the TxHDLCClk_0
clock output signal.
If the XRT94L31 has been configured to operate in the ATM UNI
Mode - TXGFC_0 (Transmit GFC data - Channel 0)
This input pin will only function in this role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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