REV. 1.0.1 A11 STS1TXA_0_D5TXH DLCDAT_0_5TXDS3 FP_0 I/O TTL/ CMOS Transmit STS-1 Te" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 77/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標準包裝： 24
應用： 網(wǎng)絡切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應商設備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
48
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
A11
STS1TXA_0_D5TXH
DLCDAT_0_5TXDS3
FP_0
I/O
TTL/
CMOS
Transmit STS-1 Telecom Bus Interface - Channel 0 - Input Data Bus
pin number 5/Transmit High-Speed HDLC Controller Input Interface
block - Channel 0 - Input Data Bus - Pin 5/Transmit DS3/E3 Frame
Boundary Indicator Output - Channel 0:
The function of this pin depends upon whether or not the STS-1 Telecom
Bus Interface, associated with Channel 0 is enabled.
If STS-1 Telecom Bus (Channel 0) has been enabled - Transmit STS-
1 Telecom Bus Interface - Input Data Bus pin number 5 -
STS1TXA_0_D5:
This input pin along with STS1TXA_0_D[7:6] and STS1TXA_0_D[4:0]
function as the Transmit (Add) STS-1 Telecom Bus Interface - Input Data
Bus for Channel 0. The Transmit STS-1 Telecom Bus interface will sam-
ple and latch this pin upon the falling edge of STS1TXA_CLK_0.
If the STS-1 Telecom Bus Interface (associated with Channel 0) has
been disabled:
This input/output pin can function in either of the following roles, depend-
ing upon which mode the XRT94L31 has been configured to operate in,
as described below.
If the XRT94L31 has been configured to operate in the High-Speed
HDLC Controller over DS3/STS-3 Mode - Transmit High-Speed HDLC
Controller Input Interface block - Channel 0 - Data Bus Input pin # 5 -
TxHDLCDAT_0_5:
If the XRT94L31 is configured to operate in the High-Speed HDLC
Controller over DS3/STS-3 Mode, then this input pin will function as
Bit 5 within the Transmit High-Speed HDLC Controller Input Inter-
face block - Input Data Bus (e.g., the TxHDLCDat_0[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block will pro-
vide the System-Side Terminal equipment with a byte-wide Transmit
High-Speed HDLC Controlller clock output signal (TxHDLCClk_0).
The Transmit High-Speed HDLC Controller Input Interface block will
sample the data residing on this input pin (along with the rest of the
TxHDLCDat_0[7:0] input pins) upon the rising edge of the TxHDLCClk_0
clock output signal.
If the XRT94L31 is configured to operate in the Clear-Channel DS3/E3
Framer over STS-3/STM-1 Mapper Mode - Transmit DS3/E3 Frame
Boundary Indicator Output - Channel 0 - TxDS3FP_0:
This output pin is pulse "High" for one DS3 or E3 clock period, when the
Transmit Payload Data Input Interface block of Channel 0 (within the
XRT94L31) is processing the last bit of a given DS3 or E3 frame.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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