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參數(shù)資料
| 型號： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 18/133頁 |
| 文件大小： | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標準包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
114
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
1.3.9
Egress Timing for STS-1/STM-0 Applications (Continued)
Table 18 presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Egress Direction) for STS-1/STM-0 Applications and when the Transmit STS-1 TOH Processor block has been
configured to output the DS3/E3/STS_1_DATA_OUT signal upon the falling edge of DS3/E3/
STS_1_CLOCK_OUT.
1.4
STS-1/STM-0 TELECOM BUS INTERFACE TIMING INFORMATION
STS-1/STM-0 Telecom Bus Interface Timing Information
This section presents the timing requirements for the STS-1/STM-0 Telecom Bus Interface. In particular this
section indicates the following.
a. Identifies which edge of RxD_CLK in which the RxD_D[7:0], RxD_PL, RxD_C1J1, RxD_ALARM and
RxD_DP output pins are updated on.
b. The clock to output delays (from the rising edge of RxD_CLK to the instant that the RxD_D[7:0], RxD_PL,
RxD_C1J1, RxD_ALARM and RxD_DP output pins are updated.
c. Identifies which edge of TxA_CLK that the TxA_D[7:0], TxA_PL, TxA_C1J1 and TxA_DP input pins are
sampled on.
d. The set-up time requirements (from an update in the TxA_D[7:0], TxA_PL, TxA_C1J1, TxA_ALARM and
TxA_DP input signals to the rising edge of TxA_CLK).
e. The hold-time requirements (from the rising edge of TxA_CLK to a change in the TxA_D[7:0], TxA_PL,
TxA_C1J1, TxA_ALARM and TxA_DP input signals)
1.4.1
SOME NOTES ABOUT THE STS-1/STM-0 TELECOM BUS INTERFACE
1.
In contrast to the names that are given to the Transmit and Receive STS-3/STM-1 Telecom Bus
Interface, the Transmit STS-1/STM-0 Telecom Bus interface will have the responsibility of receiving (in
lieu of transmitting) STS-1/STM-0 data from some remote entity over a Telecom Bus Interface that is
clocked at 6.48MHz.
Likewise, the Receive STS-1/STM-0 Telecom Bus Interface will have the
responsibility of transmitting (in lieu of receiving) STS-1/STM-0 data to some remote entity over a
Telecom Bus Interface that is also clocked at 6.48MHz.
2.
The STS-1/STM-0 Telecom Bus Interface, associated with Channel 0 can be configured to operate as
either an STS-1/STM-0 or an STS-3/STM-1 Telecom Bus Interface. Timing Information for either of
these modes will be presented in this section.
1.4.2
The Receive STS-1/STM-0 Telecom Bus Interface Timing
In the Receive STS-1/STM-0 Telecom Bus Interface, all of the signals (which are output via this Bus Interface)
are updated upon the rising edge of RxD_CLK (6.48MHz clock signal).
TABLE 17: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0
APPLICATIONSAPPLICATIONS(RISING EDGE OF DS3/E3/STS_1_CLOCK_OUT)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t11
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
output delay
0ns
4.5ns
TABLE 18: TIMING INFORMATION FOR THE EGRESS DS3/E3/STS-1 LIU INTERFACE FOR STS-1/STM-0
APPLICATIONSAPPLICATIONS(FALLING EDGE OF DS3/E3/STS_1_CLOCK_OUT)
SYMBOL
DESCRIPTION
MIN.
TYP.
MAX.
t11
Rising edge of DS3/E3/STS_1_CLK_OUT to DS3/E3/STS_1_DATA_OUT
output delay
0ns
3.3ns
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