REV. 1.0.1 M27 TXUCLK/TXPCLK I TTL For Mapper applications, please connect this pin" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 64/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
36
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
M27
TXUCLK/TXPCLK
I
TTL
For Mapper applications, please connect this pin to GND.
STS-1 TELECOM BUS INTERFACE - TRANSMIT DIRECTION
C14
E19
AC14
STS1TXA_CK_0
TXSENDFCS_0
TXGFCCLK_0
STS1TXA_CK_1
TXSENDFCS_1
TXGFCCLK_1
STS1TXA_CK_2
TXSENDFCS_2
TXGFCCLK_2
I
O
TTL
CMOS
STS-1 Transmit Telecom Bus Clock Input pin/Transmit High-Speed
HDLC Controller Input Interface Block - Send FCS Command Input
pin - Channel n (n=0,1,2):
The function of this input pin depends upon whether or not the STS-1
Telecom Bus Interface for Channel n has been enabled.
If STS-1 Telecom Bus (Channel n) has been enabled -
STS1TXA_CLK_[0:3] - Transmit STS-1 Telecom Bus Interface Block
Transmit Clock Input - Channel n:
This input clock signal functions as the clock source for the Transmit
STS-1 Telecom Bus, associated with Channel n. All input signals (e.g.,
STS1TXA_ALARM_n, STS1TXA_D_n[7:0], STS1TXA_DP_n,
STS1TXA_PL_n, STS1TXA_C1J1_n) are sampled upon the falling edge
of this input clock signal.This clock signal should operate at 19.44MHz.
(For STS-3 mode) or 6.48MHz (for STS-1 mode).
If STS-1 Telecom Bus (Channel n) has NOT been enabled:
If STS-1 Telecom Bus (Channel n) has not been enabled, then this par-
ticular pin can be configured to function in either of the following roles.
TXSENDFCS_n (Transmit High-Speed HDLC Controller Input Inter-
face block Send FCS Command Input - Channel n - High-Speed
HDLC Controller Mode Only)
The user's terminal equipment is expected to control both this input pin
and the TXSENDMSG_0 input pin during the construction and transmis-
sion of each outbound HDLC frame.
This input pin is used to command the Transmit HDLC Controller block
to compute and insert the computed FCS value into the back-end of the
outbound HDLC frame as a trailer.
If the user has configured the Transmit HDLC Controller to compute and
insert a CRC-16 value into the outbound HDLC frame, then the terminal
equipment is expected to pull this input pin "High" for two periods of
TxHDLCClk_n.
Likewise, if the user has configured the Transmit HDLC Controller to
compute and insert a CRC-32 value into the outbound HDLC frame,
then the terminal equipment is expected to pull this input pin "High" for
four periods of TxHDLCClk_n.
TXGFCCLK_n (Transmit GFC Nibble-Field Input Port clock signal
Input) - ATM Applications ONLY.
This pin only functions in this particular role if the XRT94L31 has been
configured to operate in the ATM UNI Mode.
NOTE: The user should tie this pin to GND if the DS3/E3 Framer block
has NOT been configured to operate in the High-Speed HDLC
Controller Mode.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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