REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC C7 TXPOH I TTL Transmit Path Overhead Input Port - Input pin. This pin i" />
參數(shù)資料
型號： XRT94L31IB-L
廠商： Exar Corporation
文件頁數(shù)： 52/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標準包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
25
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
C7
TXPOH
I
TTL
Transmit Path Overhead Input Port - Input pin.
This pin is used for the Transmit AU-4/VC-4 Mapper POH Processor
Block when TUG-3 mapping is used.This input pin is used to insert the
POH data into the Transmit AU-4/VC-4 Mapper POH Processor blocks
for insertion and transmission via the outbound STS-3 signal.In this
mode, the external circuitry (which is being interfaced to the Transmit
Path Overhead Input Port is suppose to monitor the following output
pins;
TxPOHFrame_n
TxPOHEnable_n
TxPOHClk_n
The TxPOHFrame_n output pin will toggle "High" upon the rising edge of
TxPOHClk_n approximately one TxPOHClk_n period prior to the TxPOH
port being ready to accept and process the first bit within J1 byte (e.g.,
the first POH byte). The TxPOHFrame_n output pin will remain "High"
for eight consecutive TxPOHClk_n periods. The external circuitry should
use this pin to note STS-1 SPE frame boundaries.
The TxPOHEnable_n output pin will toggle "High" upon the rising edge
of TxPOHClk_n approximately one TxPOHClk_n period prior to the
TxPOH port being ready to accept and process the first bit within a given
POH byte. To externally insert a given POH byte:
a. assert the TxPOHIns_n input pin by toggling it "High", and
b. place the value of the first bit (within this particular POH byte) on
this input pin upon the very next rising edge of TxPOHClk_n.
This data bit will be sampled upon the very next falling edge of
TxPOHClk_n. The external circuitry should continue to keep the
TxPOHIns_n input pin "High" and advancing the next bits (within the
POH bytes) upon each rising edge of TxPOHClk_n.
D9
TXPOHCLK
O
TTL
Transmit Path Overhead Input Port - Clock Output pin:
This pin is used for the Transmit AU-4/VC-4 Mapper POH Processor
Block when TUG-3 mapping is used.
This output pin, along with TxPOH, TxPOHEnable, TxPOHIns and
TxPOHFrame function as the Transmit Path Overhead (TxPOH) Input
Port.
The TxPOHFrame and TxPOHEnable output pins are updated upon the
falling edge this clock output signal. The TxPOHIns input pins and the
data residing on the TxPOH input pins are sampled upon the next falling
edge of this clock signal.
B5
TXPOHFRAME
O
TTL
Transmit Path Overhead Input Port - Frame Output pin:
This pin is used for the Transmit AU-4/VC-4 Mapper POH Processor
Block when TUG-3 mapping is used.
This output pin, along with the TxPOH, TxPOHEnable, TxPOHIns and
TxPOHClk function as the Transmit Path Overhead Input Port.If the user
is only inserting POH data via these input pins:
NOTE: In this mode, the TxPOH port will pulse these output pins "High"
whenever it is ready to accept and process the J1 byte (e.g., the
very first POH byte) via this port.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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