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| 型號(hào)： | XRT94L31IB-L |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 124/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER DS3/E3/STS-1 504TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 網(wǎng)絡(luò)切換 |
| 接口： | 總線 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 封裝/外殼： | 504-LBGA |
| 供應(yīng)商設(shè)備封裝： | 504-TBGA（35x35） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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XRT94L31
90
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
H5
REFSEL_L
I
TTL
Clock Synthesizer Block Select:
This input pin is used to configure the Transmit SONET circuitry (within
the XRT94L31) to use either of the following clock signals as its timing
source.a.
a. The Directly-Applied 19.44MHz clock signal, which is applied to
the REFTTL input pin (P1) or,b.
b. The output of the Clock Synthesizer block (within the chip).
Setting this input pin "High" configures the Transmit SONET circuitry
within the XRT94L31 to use the Clock Synthesizer block as its timing
source. In this mode, the user can supply either a 19.44MHz,
38.88MHz, 51.84MHz or 77.76MHz clock signal to the REFTTL input
pin.
Setting this input pin "Low" by-passes the Clock Synthesizer block. In
this case, the user MUST supply a 19.44MHz clock signal to the
REFTTL input pin in order to insure proper performance.
K4
SFM
I
TTL
Single Frequency Mode (SFM) Select:
This input pin is used to configure the three Jitter Attenuator (SONET/
SDH De-Sync) blocks of the XRT94L31 to operate in the Single-Fre-
quency Mode (SFM). If the XRT94L31 has been configured to operate
in the SFM Mode, then the user only needs to supply a 12.288MHz clock
signal to the REFCLK51 input pin. In this case, the user does not need
to supply a 44.736MHz clock signal to the REFCLK45 input pin, nor a
34.368MHz clock signal to the REFCLK34 input pin. The SFM PLL
(within the XRT94L31) will internally synthesize the appropriate
44.736MHz, 34.368MHz or 51.84MHz clock signals, and will route these
signals to the appropriate channels (within the chip) depending upon the
data rate that they are configured to operate in.
Setting this input pin to a logic "Low" disables the Single-Frequency
Mode. In this mode, the user must supply all of the appropriate frequen-
cies to the REFCLK34, REFCLK45 and REFCLK51 input pins.
Setting this input pin to a logic "High" configures the XRT94L31 to oper-
ate in the Single-Frequency Mode.
J3
Test Mode
I
TTL
Test Mode Input Pin:
Connect this input pin "Low" for normal operation.
G2
FL_TSTCLK
O
CMOS
JA Testing Clock:
This pin is used for JA testing purposes.
J2
ANALOG
O
ANA-
LOG
Analog Output Pin:
This output analog pin is used for testing purposes.
N1
VDCTST1
O
ANA-
LOG
DC Test Pin:
This pin is used for internal DC test, for example, it can be used to test
for DC current, DC voltage.
N2
VDCTST2
O
ANA-
LOG
DC Test Pin:
This pin is used for internal DC test, for example, it can be used to test
for DC current, DC voltage.
NO-CONNECT PINS
K1
N/C
AA1
N/C
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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| XRT94L33 | 制造商:EXAR 制造商全稱:EXAR 功能描述:-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS |
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| XRT94L33_2 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS |
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