參數(shù)資料
型號: TMS320DM355_07
廠商: Texas Instruments, Inc.
英文描述: Digital Media System-on-Chip (DMSoC)
中文描述: 數(shù)字媒體系統(tǒng)芯片(DMSoC)
文件頁數(shù): 79/158頁
文件大小: 1319K
代理商: TMS320DM355_07
www.ti.com
P
3.9.2
Software Controlled Pin Multiplexing
3.10 Device Reset
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding
1101(NAND)
GPIO[54]
GPIO[55]
GPIO[56]
EM_A[1]
EM_A[2]
GPIO[57]
GPIO[58]
GPIO[59]
GPIO[60]
GPIO[61]
GPIO[62]
GPIO[63]
GPIO[64]
GPIO[65]
GPIO[66]
GPIO[67]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
1100
GPIO[54]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
1010 (OneNAND)
EM_A[14]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
1000 (8-bit SRAM)
EM_BA[0]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
0010 (16-bit SRAM)
EM_A[14]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
EM_D[14]
EM_D[15]
0000
EM_BA[0]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
EM_D[14]
EM_D[15]
All pin multiplexing options are configurable by software via pin mux registers that reside in the System
Control Module. The PinMux0 Register controls the Video In muxing, PinMux1 register controls Video Out
signals, PinMux2 register controls AEMIF signals, PinMux3 registers control the multiplexing of the GIO
signals, the PinMux4 register controls the SPI and MMC/SD0 signals. Refer to the ARM Subsystem User's
Guide for complete descriptions of the pin mux registers.
There are five types of reset in DM355. The types of reset differ by how they are initiated and/or by their
effect on the chip. Each type is briefly described in
Table 3-14
and further described in the ARM
Subsystem Guide.
Table 3-14. Reset Types
Type
POR (Power-On-Reset)
Initiator
RESET pin low and TRST low
Effect
Total reset of the chip (cold reset). Resets all modules
including memory and emulation.
Resets all modules including memory, except ARM
emulation.
Same effect as warm reset.
Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory
contents and does not affect or reset clocks or power
states.
Warm Reset
RESET pin low and TRST high (initiated by ARM
emulator).
ARM emulator or Watchdog Timer (WDT).
ARM emulator
Max Reset
System Reset
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