參數(shù)資料
型號： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 124/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
P
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
17
VCTL
(B)
VDATA
(C)
19
18
22
21
23
24
25
26
VCLKIN
(A)
A. VCLKIN = PCLK or EXTCLK
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:3], G[7:2], and B[7:3]
20
20
TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK
(1)(2)
(see
Figure 5-30
)
DM355
MIN
13.33
5.7
5.7
NO.
PARAMETER
UNIT
MAX
160
17
18
19
20
21
22
23
24
25
26
t
c(VCLK)
t
w(VCLKH)
t
w(VCLKL)
t
t(VCLK)
t
d(VCLKINH-VCLKH)
t
d(VCLKINL-VCLKL)
t
d(VCLK-VCTLV)
t
d(VCLK-VCTLIV)
t
d(VCLK-VDATAV)
t
d(VCLK-VDATAIV)
Cycle time, VCLK
Pulse duration, VCLK high
Pulse duration, VCLK low
Transition time, VCLK
Delay time, VCLKIN high to VCLK high
Delay time, VCLKIN low to VCLK low
Delay time, VCLK edge to VCTL valid
Delay time, VCLK edge to VCTL invalid
Delay time, VCLK edge to VDATA valid
Delay time, VCLK edge to VDATA invalid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
2
2
12
12
4
0
4
0
(1)
The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
VCLKIN = PCLK or EXTCLK. For timing specifications relating to PCLK, see
Table 5-17
,
Timing Requirements for VPFE PCLK
Master/Slave Mode
.
(2)
Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK
5.9.2.4
DAC and Video Buffer Electrical Data/Timing
The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer
configuration. In the DAC only configuration the internal video buffer is not used and an external video
buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video
buffer are both used and a TV cable may be attached directly to the output of the video buffer. See
Figure 5-31
and
Figure 5-32
for recommenced circuits for each configuration.
DM355 Peripheral Information and Electrical Specifications
124
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