參數(shù)資料
型號(hào)： TMS320DM355_07
廠商： Texas Instruments, Inc.
英文描述： Digital Media System-on-Chip (DMSoC)
中文描述： 數(shù)字媒體系統(tǒng)芯片（DMSoC）
文件頁數(shù)： 108/158頁
文件大?。?/td> 1319K
代理商： TMS320DM355_07
www.ti.com
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
SPRS463B–SEPTEMBER 2007–REVISED OCTOBER 2007
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (see
Figure 5-14
and
Figure 5-15
) (continued)
DM355
UNI
T
NO.
PARAMETER
MIN
Nom
MAX
Output setup time, EM_BA[1:0] valid to
EM_OE low
Output hold time, EM_OE high to
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
EM_OE low
Output hold time, EM_OE high to
EM_A[13:0] invalid
EM_OE active low width (EW = 0)
EM_OE active low width (EW = 1)
Delay time from EM_WAIT deasserted to
EM_OE high
6
t
su(EMBAV-EMOEL)
(RS)*E
ns
7
t
h(EMOEH-EMBAIV)
(RH)*E
ns
8
t
su(EMBAV-EMOEL)
(RS)*E
ns
9
t
h(EMOEH-EMAIV)
(RH)*E
ns
(RST)*E
ns
ns
10
t
w(EMOEL)
(RST+(EWC*16))*E
t
d(EMWAITH-
EMOEH)
11
4E
ns
READS (OneNAND Synchronous Burst Read)
MH
z
ns
32
f
c(EM_CLK)
Frequency, EM_CLK
1
66
33
t
c(EM_CLK)
t
su(EM_ADVV-
EM_CLKH)
t
h(EM_CLKH-
EM_ADVIV)
t
su(EM_AV-
EM_CLKH)
t
h(EM_CLKH-
EM_AIV)
t
w(EM_CLKH)
t
w(EM_CLKL)
Cycle time, EM_CLK
Output setup time, EM_ADV valid before
EM_CLK high
Output hold time, EM_CLK high to EM_ADV
invalid
Output setup time, EM_A[13:0]/EM_BA[1]
valid before EM_CLK high
Output hold time, EM_CLK high to
EM_A[13:0]/EM_BA[1] invalid
Pulse duration, EM_CLK high
Pulse duration, EM_CLK low
15
1000
34
5
ns
35
6
ns
36
5
ns
37
6
ns
38
39
t
c(EM_CLK)
/3
t
c(EM_CLK)
/3
ns
ns
WRITES
EMIF write cycle time (EW = 0)
(WS+WST+WH)*E
(WS+WST+WH+(EW
ns
15
t
c(EMWCYCLE)
EMIF write cycle time (EW = 1)
ns
C*16))*E
Output setup time, EM_CE[1:0] low to
EM_WE low (SS = 0)
Output setup time, EM_CE[1:0] low to
EM_WE low (SS = 1)
Output hold time, EM_WE high to
EM_CE[1:0] high (SS = 0)
Output hold time, EM_WE high to
EM_CE[1:0] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
EM_WE low
Output hold time, EM_WE high to
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
EM_WE low
Output hold time, EM_WE high to
EM_A[13:0] invalid
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
Delay time from EM_WAIT deasserted to
EM_WE high
Output setup time, EM_D[15:0] valid to
EM_WE low
(WS)*E
ns
16
t
su(EMCEL-EMWEL)
0
ns
(WH)*E
ns
17
t
h(EMWEH-EMCEH)
0
ns
20
t
su(EMBAV-EMWEL)
(WS)*E
ns
21
t
h(EMWEH-EMBAIV)
(WH)*E
ns
22
t
su(EMAV-EMWEL)
(WS)*E
ns
23
t
h(EMWEH-EMAIV)
(WH)*E
ns
(WST)*E
ns
ns
24
t
w(EMWEL)
(WST+(EWC*16))*E
t
d(EMWAITH-
EMWEH)
25
4E
ns
26
t
su(EMDV-EMWEL)
(WS)*E
ns
DM355 Peripheral Information and Electrical Specifications
108
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